diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml
index fea61541c..187a3e474 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_dsp8_nonLR_caravel_io_skywater130nm.xml
@@ -210,7 +210,8 @@
- mult_8.a[0:5] mult_8.b[0:5] mult_8.out[0:10]
+ mult_8.a[0:2] mult_8.b[0:2] mult_8.out[0:5]
+ mult_8.a[3:5] mult_8.b[3:5] mult_8.out[6:10]
mult_8.a[6:7] mult_8.b[6:7] mult_8.out[11:15]
diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm.xml
index 2d817e7cd..fd23eb91e 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_softadder_register_scan_chain_frac_dsp16_nonLR_caravel_io_skywater130nm.xml
@@ -219,10 +219,10 @@
mult_16.a[0:2] mult_16.b[0:2] mult_16.out[0:5]
mult_16.a[3:5] mult_16.b[3:5] mult_16.out[6:10]
-
+ mult_16.a[6:7] mult_16.b[6:7] mult_16.out[11:15]
mult_16.a[8:10] mult_16.b[8:10] mult_16.out[16:21]
mult_16.a[11:13] mult_16.b[11:13] mult_16.out[22:26]
- mult_16.a[6:7] mult_16.b[6:7] mult_16.out[11:15] mult_16.a[14:15] mult_16.b[14:15] mult_16.out[27:31]
+ mult_16.a[14:15] mult_16.b[14:15] mult_16.out[27:31]
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
index 2cef83e5c..12b9dd0b8 100755
--- a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
@@ -821,9 +821,35 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids,
opin_grid_side[1] = NUM_SIDES;
}
- /* SideManager: TOP => 0, RIGHT => 1, BOTTOM => 2, LEFT => 3 */
+ /* Add IPIN nodes from adjacent grids: the 4 grids sitting on the 4 corners of the Switch Block
+ *
+ * - The concept of top/bottom side of connection block in GSB domain:
+ *
+ * | Grid[x][y+1] |
+ * | BOTTOM side |
+ * +-----------------------+
+ * |
+ * v
+ * +-----------------------+
+ * | TOP side |
+ * | X- Connection Block |
+ * | BOTTOM side |
+ * +-----------------------+
+ * ^
+ * |
+ * +-----------------------+
+ * | TOP side |
+ * | Grid[x][y] |
+ *
+ * - The concept of top/bottom side of connection block in GSB domain:
+ *
+ * ---------------+ +---------------------- ... ---------------------+ +----------------
+ * Grid[x][y+1] |->| Y- Connection Block Y- Connection Block |<-| Grid[x+1][y+1]
+ * RIGHT side | | LEFT side ... RIGHT side | | LEFT side
+ * --------------+ +---------------------- ... ---------------------+ +----------------
+ *
+ */
for (size_t side = 0; side < rr_gsb.get_num_sides(); ++side) {
- /* Local variables inside this for loop */
SideManager side_manager(side);
size_t ix;
size_t iy;
@@ -832,42 +858,34 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids,
enum e_side ipin_rr_node_grid_side;
switch (side) {
- case TOP: /* TOP = 0 */
- /* For the bording, we should take special care */
- /* Check if left side chan width is 0 or not */
+ case TOP:
+ /* Consider the routing channel that is connected to the left side of the switch block */
chan_side = LEFT;
- /* Build the connection block: ipin and ipin_grid_side */
- /* BOTTOM side INPUT Pins of Grid[x][y+1] */
+ /* The input pins of the routing channel come from the bottom side of Grid[x][y+1] */
ix = rr_gsb.get_sb_x();
iy = rr_gsb.get_sb_y() + 1;
ipin_rr_node_grid_side = BOTTOM;
break;
- case RIGHT: /* RIGHT = 1 */
- /* For the bording, we should take special care */
- /* Check if TOP side chan width is 0 or not */
+ case RIGHT:
+ /* Consider the routing channel that is connected to the top side of the switch block */
chan_side = TOP;
- /* Build the connection block: ipin and ipin_grid_side */
- /* LEFT side INPUT Pins of Grid[x+1][y+1] */
+ /* The input pins of the routing channel come from the left side of Grid[x+1][y+1] */
ix = rr_gsb.get_sb_x() + 1;
iy = rr_gsb.get_sb_y() + 1;
ipin_rr_node_grid_side = LEFT;
break;
- case BOTTOM: /* BOTTOM = 2*/
- /* For the bording, we should take special care */
- /* Check if left side chan width is 0 or not */
+ case BOTTOM:
+ /* Consider the routing channel that is connected to the left side of the switch block */
chan_side = LEFT;
- /* Build the connection block: ipin and ipin_grid_side */
- /* TOP side INPUT Pins of Grid[x][y] */
+ /* The input pins of the routing channel come from the top side of Grid[x][y] */
ix = rr_gsb.get_sb_x();
iy = rr_gsb.get_sb_y();
ipin_rr_node_grid_side = TOP;
break;
- case LEFT: /* LEFT = 3 */
- /* For the bording, we should take special care */
- /* Check if left side chan width is 0 or not */
+ case LEFT:
+ /* Consider the routing channel that is connected to the top side of the switch block */
chan_side = TOP;
- /* Build the connection block: ipin and ipin_grid_side */
- /* RIGHT side INPUT Pins of Grid[x][y+1] */
+ /* The input pins of the routing channel come from the right side of Grid[x][y+1] */
ix = rr_gsb.get_sb_x();
iy = rr_gsb.get_sb_y() + 1;
ipin_rr_node_grid_side = RIGHT;