fixing minor bugs

vpr7_rram/libarchfpga/fpga_spice_include/linkedlist.h

@@ -25,6 +25,8 @@ t_llist* search_llist_tail(t_llist* head);
 
 int find_length_llist(t_llist* head);
 
+boolean check_dptr_exist_in_llist(t_llist* head, void* data_ptr);
+
 void free_llist(t_llist* head);
 
 t_llist* reverse_llist(t_llist* head);

vpr7_rram/libarchfpga/linkedlist.c

@@ -135,6 +135,25 @@ int find_length_llist(t_llist* head) {
   return length;
 }
 
+/* Search the linked list and check if dptr has been stored in a node */
+boolean check_dptr_exist_in_llist(t_llist* head, void* data_ptr) {
+  t_llist* temp = head;
+
+  if (NULL == temp) {
+  /* A NULL head means zero length */
+    return FALSE;
+  }
+
+  while (temp != NULL) {
+    if (data_ptr == temp->dptr) {
+      return TRUE;
+    }
+    temp = temp->next;
+  }
+
+  return FALSE;
+}
+
 /* Free a linked list, Make sure before this function,
  * the dptr has been freed! I cannot free them here!!!
  */

vpr7_rram/vpr/SRC/fpga_spice/base/fpga_spice_utils.c

@@ -7428,3 +7428,57 @@ void get_mapped_lut_pb_input_pin_vpack_net_num(t_pb* lut_pb,
   return;
 }
 
+/* Recursively find all the global ports in the spice_model / sub spice_model 
+ */
+void rec_stats_spice_model_global_ports(t_spice_model* cur_spice_model,
+                                        boolean recursive,
+                                        t_llist** spice_model_head) {
+  int iport;
+  t_llist* temp = NULL;
+
+  /* Check */
+  assert(NULL != cur_spice_model);
+  if (0 < cur_spice_model->num_port) {
+    assert(NULL != cur_spice_model->ports);
+  }
+
+  for (iport = 0; iport < cur_spice_model->num_port; iport++) {
+    /* if this spice model requires customized netlist to be included, we do not go recursively */
+    if (TRUE == recursive) { 
+      /* GO recursively first, and meanwhile count the number of global ports */
+      /* For the port that requires another spice_model, i.e., SRAM
+       * We need include any global port in that spice model
+       */
+      if (NULL != cur_spice_model->ports[iport].spice_model) {
+         rec_stats_spice_model_global_ports(cur_spice_model->ports[iport].spice_model, 
+                                            recursive, spice_model_head);
+      }
+    }
+    /* By pass non-global ports*/
+    if (FALSE == cur_spice_model->ports[iport].is_global) {
+      continue;
+    }
+    /* Now we have a global port, add it to linked list */
+    assert (TRUE == cur_spice_model->ports[iport].is_global);
+    if (NULL == (*spice_model_head)) {
+     (*spice_model_head) = create_llist(1);
+     /* Configure the data pointer of linked list */
+     (*spice_model_head)->dptr = (void*) (&cur_spice_model->ports[iport]);
+     /* Check if this ports exists in the linked list */
+    } else if (FALSE == check_dptr_exist_in_llist((*spice_model_head),
+                                                  (void*)(&cur_spice_model->ports[iport]))) {
+      /* Non-exist in the current linked-list, a new node is required 
+       * Go to the tail of the linked-list and add a new node  
+       */
+      temp = search_llist_tail(*spice_model_head);
+      temp = insert_llist_node(temp);
+      /* Configure the data pointer of linked list */
+      temp->dptr = (void*) (&cur_spice_model->ports[iport]);
+    }
+  }
+
+  return;
+}
+
+
+

vpr7_rram/vpr/SRC/fpga_spice/base/fpga_spice_utils.h

@@ -638,3 +638,7 @@ boolean check_subckt_file_exist_in_llist(t_llist* subckt_llist_head,
 
 void get_mapped_lut_pb_input_pin_vpack_net_num(t_pb* lut_pb,
                                                int* num_lut_pin, int** lut_pin_net);
+
+void rec_stats_spice_model_global_ports(t_spice_model* cur_spice_model,
+                                        boolean recursive,
+                                        t_llist** spice_model_head);

vpr7_rram/vpr/SRC/fpga_spice/verilog/verilog_submodules.c

@@ -804,11 +804,13 @@ void dump_verilog_mux_basis_module(FILE* fp,
   init_spice_mux_arch(spice_mux_model->spice_model, spice_mux_model->spice_mux_arch, spice_mux_model->size);
 
   /* Corner case: Error out  MUX_SIZE = 2, automatcially give a one-level structure */
+  /*
   if ((2 == spice_mux_model->size)&&(SPICE_MODEL_STRUCTURE_ONELEVEL != spice_mux_model->spice_model->design_tech_info.structure)) {
     vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Structure of SPICE model (%s) should be one-level because it is linked to a 2:1 MUX!\n",
                __FILE__, __LINE__, spice_mux_model->spice_model->name);
     exit(1);
   }
+  */
 
   /* Prepare the basis subckt name:
    */
@@ -1740,11 +1742,13 @@ void dump_verilog_mux_module(FILE* fp,
   }
 
   /* Corner case: Error out  MUX_SIZE = 2, automatcially give a one-level structure */
+  /*
   if ((2 == spice_mux_model->size)&&(SPICE_MODEL_STRUCTURE_ONELEVEL != spice_mux_model->spice_model->design_tech_info.structure)) {
     vpr_printf(TIO_MESSAGE_ERROR, "(File:%s,[LINE%d])Structure of SPICE model (%s) should be one-level because it is linked to a 2:1 MUX!\n",
                __FILE__, __LINE__, spice_mux_model->spice_model->name);
     exit(1);
   }
+  */
 
   /* Print the definition of subckt*/
   /* Check the design technology*/