From 645db17168268a300e78d57a26191c54a16c78a7 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Wed, 23 Sep 2020 17:52:59 -0600
Subject: [PATCH] [Architecture] Patch DFF Verilog HDL

---
 openfpga_flow/VerilogNetlists/ff_en.v | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/openfpga_flow/VerilogNetlists/ff_en.v b/openfpga_flow/VerilogNetlists/ff_en.v
index fa0ed47d4..c7a063ce7 100644
--- a/openfpga_flow/VerilogNetlists/ff_en.v
+++ b/openfpga_flow/VerilogNetlists/ff_en.v
@@ -13,6 +13,7 @@ input CK, // Clock Input
 /* Local ports follow */
 input D, // Data Input
 output Q // Q output
+output QB // QB output
 );
 //------------Internal Variables--------
 reg q_reg;
@@ -27,7 +28,13 @@ end else if (WE) begin
   q_reg <= D;
 end
 
+`ifndef ENABLE_FORMAL_VERIFICATION
 // Wire q_reg to Q
 assign Q = q_reg;
+assign QB = ~q_reg;
+`else
+assign Q = 1'bZ;
+assign QB = !Q;
+`endif
 
 endmodule //End Of Module