Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev

README.md

@@ -16,8 +16,18 @@ mkdir build && cd build            # Create a folder named build in the OpenPFGA
 cmake ..  -DCMAKE_BUILD_TYPE=debug # Create a Makefile in this folder using cmake
 make                               # Compile the tool and its dependencies
 ```
-*cmake3.12 is required to use graphical interface*
+*cmake3.12 is recommended to compile OpenFPGA with GUI*
 
+**Quick Compilation Verification**
+To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository.
+```bash
+python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification --debug --show_thread_logs
+```
+
+*Python3 and iVerilog v10.1+ are required. GUI will pop-up if enabled during compilation.*
+
+
+**Supported Operating Systems**
 We currently target OpenFPGA for:
  1. Ubuntu 18.04
  2. Red Hat 7.5

openfpga_flow/scripts/run_fpga_flow.py

@@ -80,6 +80,8 @@ parser.add_argument('--run_dir', type=str,
                     help="Directory to store intermidiate file & final results")
 parser.add_argument('--yosys_tmpl', type=str,
                     help="Alternate yosys template, generates top_module.blif")
+parser.add_argument('--disp', action="store_true",
+                    help="Open display while running VPR")
 parser.add_argument('--debug', action="store_true",
                     help="Run script in debug mode")
 
@@ -582,9 +584,9 @@ def run_vpr():
     ExecTime["VPRStart"] = time.time()
     # Format the BLIF File
     cmd = r"mv %s.blif %s.blif.bak && cat %s.blif.bak" % (
-                                args.top_module,
-                                args.top_module,
-                                args.top_module)
+        args.top_module,
+        args.top_module,
+        args.top_module)
     cmd += r"| sed 's/$/./' | fold -s -w80 "
     cmd += r"| sed 's/[^.]$/ \\/' | sed 's/[.]$/ /'"
     cmd += " > %s.blif" % args.top_module
@@ -651,9 +653,11 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
                "--net_file", args.top_module+"_vpr.net",
                "--place_file", args.top_module+"_vpr.place",
                "--route_file", args.top_module+"_vpr.route",
-               "--full_stats", "--nodisp",
+               "--full_stats",
                "--activity_file", args.top_module+"_ace_out.act",
                ]
+    if not args.disp:
+        command += ["--nodisp"]
     if route_only:
         command += ["--route"]
     # Power options

openfpga_flow/tasks/compilation_verification/config/task.conf

@@ -0,0 +1,59 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=vpr_blif
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/template/k4_N4_sram_chain_FC_behavioral_verilog_template.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.blif
+
+[SYNTHESIS_PARAM]
+bench0_top = K4n4_test
+bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.act
+bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/test_modes/k4_N4/K4N4_test_modes.v
+bench0_chan_width = 100
+
+#[SCRIPT_PARAM_FIX_ROUTE_CHAN_WIDTH]
+#fix_route_chan_width=300
+#vpr_fpga_verilog_include_icarus_simulator=
+#vpr_fpga_verilog_formal_verification_top_netlist=
+#vpr_fpga_verilog_include_timing=
+#vpr_fpga_verilog_include_signal_init=
+#vpr_fpga_verilog_print_autocheck_top_testbench=
+#vpr_fpga_bitstream_generator=
+#vpr_fpga_verilog_print_user_defined_template=
+#vpr_fpga_verilog_print_report_timing_tcl=
+#vpr_fpga_verilog_print_sdc_pnr=
+#vpr_fpga_verilog_print_sdc_analysis=
+#vpr_fpga_x2p_compact_routing_hierarchy=
+#end_flow_with_test=
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH_0]
+min_route_chan_width=1.3
+vpr_fpga_verilog_include_icarus_simulator=
+vpr_fpga_verilog_formal_verification_top_netlist=
+vpr_fpga_verilog_include_timing=
+vpr_fpga_verilog_include_signal_init=
+vpr_fpga_verilog_print_autocheck_top_testbench=
+vpr_fpga_bitstream_generator=
+vpr_fpga_verilog_print_user_defined_template=
+vpr_fpga_verilog_print_report_timing_tcl=
+vpr_fpga_verilog_print_sdc_pnr=
+vpr_fpga_verilog_print_sdc_analysis=
+vpr_fpga_verilog_explicit_mapping=
+vpr_fpga_x2p_compact_routing_hierarchy=
+disp=
+end_flow_with_test=