[test] typo

2024-07-09 22:54:33 -07:00 · 2024-07-09 22:54:33 -07:00 · 63f2a07c86
parent 27e29f949c
commit 63f2a07c86
1 changed files with 1 additions and 1 deletions
--- a/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v
+++ b/openfpga_flow/benchmarks/micro_benchmark/rst_and_clk_on_lut/rst_and_clk_on_lut.v
@ -4,7 +4,7 @@
 ////////////////////////////////////////
 `timescale 1ns / 1ps
-module rst_on_lut(a, b, c, q, out0, out1, clk, rst);
+module rst_and_clk_on_lut(a, b, c, q, out0, out1, clk, rst);
 input wire rst;
 input wire clk;