From 63f130d948c142101af8e2ef4e562d01dafd85b2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 13 Oct 2020 12:04:07 -0600 Subject: [PATCH] [Test] Deploy none constant input test case to CI --- .travis/fpga_verilog_reg_test.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh index 73a549bd1..93b24e561 100755 --- a/.travis/fpga_verilog_reg_test.sh +++ b/.travis/fpga_verilog_reg_test.sh @@ -73,6 +73,9 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/outbuf_on echo -e "Testing Verilog generation with routing multiplexers with constant gnd input"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/const_input_gnd --debug --show_thread_logs +echo -e "Testing Verilog generation with routing multiplexers without constant inputs"; +python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/mux_design/no_const_input --debug --show_thread_logs + echo -e "Testing Verilog generation with behavioral description"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/behavioral_verilog --debug --show_thread_logs