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Update to highlight correct section of code

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bbleaptrot 2021-04-02 10:04:53 -06:00 committed by GitHub
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docs/source/tutorials/arch_modeling/open_cell_libraries_tutorial.rst
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@ -306,7 +306,7 @@ From the root directory, view the ``luts.v`` file with this command:
Scrolling through ``luts.v``, this should be present in the file: Scrolling through ``luts.v``, this should be present in the file:
.. code-block:: verilog .. code-block:: verilog
:emphasize-lines: 58,59,72,73,74,75,76,77,78,79,80 :emphasize-lines: 64,65,72,73,74,75,76,77,78,79,80
//------------------------------------------- //-------------------------------------------
// FPGA Synthesizable Verilog Netlist // FPGA Synthesizable Verilog Netlist