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[HDL] Patch dpram cell

This commit is contained in:
tangxifan 2021-04-27 23:42:31 -06:00
parent 411af10933
commit 63309ba72b
1 changed files with 4 additions and 4 deletions
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8
openfpga_flow/openfpga_cell_library/verilog/dpram_2048x8.v
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@ -9,8 +9,8 @@ module dpram_2048x8 (
input clk, input clk,
input wen, input wen,
input ren, input ren,
input[0:11] waddr, input[0:10] waddr,
input[0:11] raddr, input[0:10] raddr,
input[0:7] data_in, input[0:7] data_in,
output[0:7] data_out ); output[0:7] data_out );
@ -35,11 +35,11 @@ endmodule
module dual_port_sram ( module dual_port_sram (
input wclk, input wclk,
input wen, input wen,
input[0:11] waddr, input[0:10] waddr,
input[0:7] data_in, input[0:7] data_in,
input rclk, input rclk,
input ren, input ren,
input[0:11] raddr, input[0:10] raddr,
output[0:7] data_out ); output[0:7] data_out );
reg[0:7] ram[0:2047]; reg[0:7] ram[0:2047];