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[Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp``

This commit is contained in:
tangxifan 2022-01-25 12:09:08 -08:00
parent 0c29638bc9
commit 62b57b05d2
31 changed files with 158 additions and 78 deletions
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15
docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
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@ -28,6 +28,10 @@ write_fabric_verilog
Output a template Verilog netlist for all the user-defined ``circuit models`` in :ref:`circuit_library`. This aims to help engineers to check what is the port sequence required by top-level Verilog netlists
.. option:: --no_time_stamp
Do not print time stamp in Verilog netlists
.. option:: --verbose
Show verbose log
@ -82,6 +86,9 @@ write_full_testbench
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
.. option:: --no_time_stamp
Do not print time stamp in Verilog netlists
.. option:: --verbose
@ -133,6 +140,10 @@ __ iverilog_website_
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
.. option:: --no_time_stamp
Do not print time stamp in Verilog netlists
.. option:: --verbose
Show verbose log
@ -169,6 +180,10 @@ write_preconfigured_testbench
Specify the default net type for the Verilog netlists. Currently, supported types are ``none`` and ``wire``. Default value: ``none``.
.. option:: --no_time_stamp
Do not print time stamp in Verilog netlists
.. option:: --verbose
Show verbose log

8
openfpga/src/base/openfpga_verilog.cpp
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@ -34,6 +34,7 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_include_timing = cmd.option("include_timing");
CommandOptionId opt_print_user_defined_template = cmd.option("print_user_defined_template");
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -43,6 +44,7 @@ int write_fabric_verilog(OpenfpgaContext& openfpga_ctx,
options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_include_timing(cmd_context.option_enable(cmd, opt_include_timing));
options.set_time_stamp(!cmd_context.option_enable(cmd, opt_no_time_stamp));
options.set_print_user_defined_template(cmd_context.option_enable(cmd, opt_print_user_defined_template));
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
options.set_default_net_type(cmd_context.option_value(cmd, opt_default_net_type));
@ -80,6 +82,7 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -92,6 +95,7 @@ int write_full_testbench(const OpenfpgaContext& openfpga_ctx,
options.set_fast_configuration(cmd_context.option_enable(cmd, opt_fast_configuration));
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_time_stamp(!cmd_context.option_enable(cmd, opt_no_time_stamp));
options.set_print_top_testbench(true);
options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {
@ -134,6 +138,7 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_include_signal_init = cmd.option("include_signal_init");
CommandOptionId opt_embed_bitstream = cmd.option("embed_bitstream");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -143,6 +148,7 @@ int write_preconfigured_fabric_wrapper(const OpenfpgaContext& openfpga_ctx,
options.set_output_directory(cmd_context.option_value(cmd, opt_output_dir));
options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_time_stamp(!cmd_context.option_enable(cmd, opt_no_time_stamp));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_include_signal_init(cmd_context.option_enable(cmd, opt_include_signal_init));
options.set_print_formal_verification_top_netlist(true);
@ -186,6 +192,7 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
CommandOptionId opt_reference_benchmark = cmd.option("reference_benchmark_file_path");
CommandOptionId opt_explicit_port_mapping = cmd.option("explicit_port_mapping");
CommandOptionId opt_default_net_type = cmd.option("default_net_type");
CommandOptionId opt_no_time_stamp = cmd.option("no_time_stamp");
CommandOptionId opt_verbose = cmd.option("verbose");
/* This is an intermediate data structure which is designed to modularize the FPGA-Verilog
@ -196,6 +203,7 @@ int write_preconfigured_testbench(const OpenfpgaContext& openfpga_ctx,
options.set_fabric_netlist_file_path(cmd_context.option_value(cmd, opt_fabric_netlist));
options.set_reference_benchmark_file_path(cmd_context.option_value(cmd, opt_reference_benchmark));
options.set_explicit_port_mapping(cmd_context.option_enable(cmd, opt_explicit_port_mapping));
options.set_time_stamp(!cmd_context.option_enable(cmd, opt_no_time_stamp));
options.set_verbose_output(cmd_context.option_enable(cmd, opt_verbose));
options.set_print_preconfig_top_testbench(true);
if (true == cmd_context.option_enable(cmd, opt_default_net_type)) {

9
openfpga/src/base/openfpga_verilog_command.cpp
View File

@ -40,6 +40,9 @@ ShellCommandId add_openfpga_write_fabric_verilog_command(openfpga::Shell<Openfpg
CommandOptionId default_net_type_opt = shell_cmd.add_option("default_net_type", false, "Set the default net type for Verilog netlists. Default value is 'none'");
shell_cmd.set_option_require_value(default_net_type_opt, openfpga::OPT_STRING);
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print a time stamp in the output files");
/* Add an option '--verbose' */
shell_cmd.add_option("verbose", false, "Enable verbose output");
@ -103,6 +106,9 @@ ShellCommandId add_openfpga_write_full_testbench_command(openfpga::Shell<Openfpg
/* add an option '--include_signal_init' */
shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches");
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print a time stamp in the output files");
/* add an option '--verbose' */
shell_cmd.add_option("verbose", false, "enable verbose output");
@ -156,6 +162,9 @@ ShellCommandId add_openfpga_write_preconfigured_fabric_wrapper_command(openfpga:
/* add an option '--include_signal_init' */
shell_cmd.add_option("include_signal_init", false, "initialize all the signals in verilog testbenches");
/* Add an option '--no_time_stamp' */
shell_cmd.add_option("no_time_stamp", false, "Do not print a time stamp in the output files");
/* add an option '--verbose' */
shell_cmd.add_option("verbose", false, "enable verbose output");

9
openfpga/src/fpga_verilog/fabric_verilog_options.cpp
View File

@ -19,6 +19,7 @@ FabricVerilogOption::FabricVerilogOption() {
compress_routing_ = false;
print_user_defined_template_ = false;
default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE;
time_stamp_ = true;
verbose_output_ = false;
}
@ -33,6 +34,10 @@ bool FabricVerilogOption::include_timing() const {
return include_timing_;
}
bool FabricVerilogOption::time_stamp() const {
return time_stamp_;
}
bool FabricVerilogOption::explicit_port_mapping() const {
return explicit_port_mapping_;
}
@ -64,6 +69,10 @@ void FabricVerilogOption::set_include_timing(const bool& enabled) {
include_timing_ = enabled;
}
void FabricVerilogOption::set_time_stamp(const bool& enabled) {
time_stamp_ = enabled;
}
void FabricVerilogOption::set_explicit_port_mapping(const bool& enabled) {
explicit_port_mapping_ = enabled;
}

3
openfpga/src/fpga_verilog/fabric_verilog_options.h
View File

@ -19,6 +19,7 @@ class FabricVerilogOption {
FabricVerilogOption();
public: /* Public accessors */
std::string output_directory() const;
bool time_stamp() const;
bool include_timing() const;
bool explicit_port_mapping() const;
bool compress_routing() const;
@ -27,6 +28,7 @@ class FabricVerilogOption {
bool verbose_output() const;
public: /* Public mutators */
void set_output_directory(const std::string& output_dir);
void set_time_stamp(const bool& enabled);
void set_include_timing(const bool& enabled);
void set_explicit_port_mapping(const bool& enabled);
void set_compress_routing(const bool& enabled);
@ -40,6 +42,7 @@ class FabricVerilogOption {
bool compress_routing_;
bool print_user_defined_template_;
e_verilog_default_net_type default_net_type_;
bool time_stamp_;
bool verbose_output_;
};

11
openfpga/src/fpga_verilog/verilog_api.cpp
View File

@ -133,7 +133,8 @@ void fpga_fabric_verilog(ModuleManager &module_manager,
/* Generate an netlist including all the fabric-related netlists */
print_verilog_fabric_include_netlist(const_cast<const NetlistManager &>(netlist_manager),
src_dir_path,
circuit_lib);
circuit_lib,
options.time_stamp());
/* Given a brief stats on how many Verilog modules have been written to files */
VTR_LOGV(options.verbose_output(),
@ -193,9 +194,7 @@ int fpga_verilog_full_testbench(const ModuleManager &module_manager,
/* Generate a Verilog file including all the netlists that have been generated */
print_verilog_full_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path(),
options.no_self_checking());
options);
return status;
}
@ -284,9 +283,7 @@ int fpga_verilog_preconfigured_testbench(const ModuleManager &module_manager,
/* Generate a Verilog file including all the netlists that have been generated */
print_verilog_preconfigured_testbench_include_netlists(src_dir_path,
netlist_name,
options.fabric_netlist_file_path(),
options.reference_benchmark_file_path(),
options.no_self_checking());
options);
return status;
}

27
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.cpp
View File

@ -32,7 +32,8 @@ namespace openfpga {
*******************************************************************/
void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
const std::string& src_dir,
const CircuitLibrary& circuit_lib) {
const CircuitLibrary& circuit_lib,
const bool& include_time_stamp) {
std::string verilog_fname = src_dir + std::string(FABRIC_INCLUDE_VERILOG_NETLIST_FILE_NAME);
/* Create the file stream */
@ -43,7 +44,7 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
check_file_stream(verilog_fname.c_str(), fp);
/* Print the title */
print_verilog_file_header(fp, std::string("Fabric Netlist Summary"));
print_verilog_file_header(fp, std::string("Fabric Netlist Summary"), include_time_stamp);
/* Print preprocessing flags */
print_verilog_comment(fp, std::string("------ Include defines: preproc flags -----"));
@ -96,10 +97,11 @@ void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
*******************************************************************/
void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file,
const bool& no_self_checking) {
const VerilogTestbenchOption& options) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
std::string fabric_netlist_file = options.fabric_netlist_file_path();
std::string reference_benchmark_file = options.reference_benchmark_file_path();
bool no_self_checking = options.no_self_checking();
/* Create the file stream */
std::fstream fp;
@ -109,7 +111,7 @@ void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
check_file_stream(verilog_fname.c_str(), fp);
/* Print the title */
print_verilog_file_header(fp, std::string("Netlist Summary"));
print_verilog_file_header(fp, std::string("Netlist Summary"), options.time_stamp());
/* Include FPGA top module */
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
@ -142,10 +144,11 @@ void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
*******************************************************************/
void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file,
const bool& no_self_checking) {
const VerilogTestbenchOption& options) {
std::string verilog_fname = src_dir + circuit_name + std::string(TOP_VERILOG_TESTBENCH_INCLUDE_NETLIST_FILE_NAME_POSTFIX);
std::string fabric_netlist_file = options.fabric_netlist_file_path();
std::string reference_benchmark_file = options.reference_benchmark_file_path();
bool no_self_checking = options.no_self_checking();
/* Create the file stream */
std::fstream fp;
@ -155,7 +158,7 @@ void print_verilog_preconfigured_testbench_include_netlists(const std::string& s
check_file_stream(verilog_fname.c_str(), fp);
/* Print the title */
print_verilog_file_header(fp, std::string("Netlist Summary"));
print_verilog_file_header(fp, std::string("Netlist Summary"), options.time_stamp());
/* Include FPGA top module */
print_verilog_comment(fp, std::string("------ Include fabric top-level netlists -----"));
@ -200,7 +203,9 @@ void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
check_file_stream(verilog_fname.c_str(), fp);
/* Print the title */
print_verilog_file_header(fp, std::string("Preprocessing flags to enable/disable features in FPGA Verilog modules"));
print_verilog_file_header(fp,
std::string("Preprocessing flags to enable/disable features in FPGA Verilog modules"),
fabric_verilog_opts.time_stamp());
/* To enable timing */
if (true == fabric_verilog_opts.include_timing()) {

11
openfpga/src/fpga_verilog/verilog_auxiliary_netlists.h
View File

@ -19,19 +19,16 @@ namespace openfpga {
void print_verilog_fabric_include_netlist(const NetlistManager& netlist_manager,
const std::string& src_dir,
const CircuitLibrary& circuit_lib);
const CircuitLibrary& circuit_lib,
const bool& include_time_stamp);
void print_verilog_full_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file,
const bool& no_self_checking);
const VerilogTestbenchOption& options);
void print_verilog_preconfigured_testbench_include_netlists(const std::string& src_dir,
const std::string& circuit_name,
const std::string& fabric_netlist_file,
const std::string& reference_benchmark_file,
const bool& no_self_checking);
const VerilogTestbenchOption& options);
void print_verilog_preprocessing_flags_netlist(const std::string& src_dir,
const FabricVerilogOption& fabric_verilog_opts);

14
openfpga/src/fpga_verilog/verilog_decoders.cpp
View File

@ -166,7 +166,7 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& submodule_dir,
const e_verilog_default_net_type& default_net_type) {
const FabricVerilogOption& options) {
std::string verilog_fname(submodule_dir + std::string(LOCAL_ENCODER_VERILOG_FILE_NAME));
/* Create the file stream */
@ -179,7 +179,7 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
VTR_LOG("Writing Verilog netlist for local decoders for multiplexers '%s'...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Local Decoders for Multiplexers");
print_verilog_file_header(fp, "Local Decoders for Multiplexers", options.time_stamp());
/* Create a library for local encoders with different sizes */
DecoderLibrary decoder_lib;
@ -214,7 +214,7 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
/* Generate Verilog modules for the found unique local encoders */
for (const auto& decoder : decoder_lib.decoders()) {
print_verilog_mux_local_decoder_module(fp, module_manager, decoder_lib, decoder, default_net_type);
print_verilog_mux_local_decoder_module(fp, module_manager, decoder_lib, decoder, options.default_net_type());
}
/* Close the file stream */
@ -648,7 +648,7 @@ void print_verilog_submodule_arch_decoders(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const DecoderLibrary& decoder_lib,
const std::string& submodule_dir,
const e_verilog_default_net_type& default_net_type) {
const FabricVerilogOption& options) {
std::string verilog_fname(submodule_dir + std::string(ARCH_ENCODER_VERILOG_FILE_NAME));
/* Create the file stream */
@ -661,14 +661,14 @@ void print_verilog_submodule_arch_decoders(const ModuleManager& module_manager,
VTR_LOG("Writing Verilog netlist for configuration decoders '%s'...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Decoders for fabric configuration protocol ");
print_verilog_file_header(fp, "Decoders for fabric configuration protocol", options.time_stamp());
/* Generate Verilog modules for the found unique local encoders */
for (const auto& decoder : decoder_lib.decoders()) {
if (true == decoder_lib.use_data_in(decoder)) {
print_verilog_arch_decoder_with_data_in_module(fp, module_manager, decoder_lib, decoder, default_net_type);
print_verilog_arch_decoder_with_data_in_module(fp, module_manager, decoder_lib, decoder, options.default_net_type());
} else {
print_verilog_arch_decoder_module(fp, module_manager, decoder_lib, decoder, default_net_type);
print_verilog_arch_decoder_module(fp, module_manager, decoder_lib, decoder, options.default_net_type());
}
}

5
openfpga/src/fpga_verilog/verilog_decoders.h
View File

@ -15,6 +15,7 @@
#include "module_manager.h"
#include "netlist_manager.h"
#include "verilog_port_types.h"
#include "fabric_verilog_options.h"
/********************************************************************
* Function declaration
@ -28,13 +29,13 @@ void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_mana
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,
const std::string& submodule_dir,
const e_verilog_default_net_type& default_net_type);
const FabricVerilogOption& options);
void print_verilog_submodule_arch_decoders(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const DecoderLibrary& decoder_lib,
const std::string& submodule_dir,
const e_verilog_default_net_type& default_net_type);
const FabricVerilogOption& options);
} /* end namespace openfpga */

14
openfpga/src/fpga_verilog/verilog_essential_gates.cpp
View File

@ -505,7 +505,7 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const std::string& submodule_dir,
const CircuitLibrary& circuit_lib,
const e_verilog_default_net_type& default_net_type) {
const FabricVerilogOption& options) {
/* TODO: remove .bak when this part is completed and tested */
std::string verilog_fname = submodule_dir + std::string(ESSENTIALS_VERILOG_FILE_NAME);
@ -520,13 +520,13 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
VTR_LOG("Generating Verilog netlist '%s' for essential gates...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Essential gates");
print_verilog_file_header(fp, "Essential gates", options.time_stamp());
/* Print constant generators */
/* VDD */
print_verilog_constant_generator_module(module_manager, fp, 0, default_net_type);
print_verilog_constant_generator_module(module_manager, fp, 0, options.default_net_type());
/* GND */
print_verilog_constant_generator_module(module_manager, fp, 1, default_net_type);
print_verilog_constant_generator_module(module_manager, fp, 1, options.default_net_type());
for (const auto& circuit_model : circuit_lib.models()) {
/* By pass user-defined modules */
@ -534,15 +534,15 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
continue;
}
if (CIRCUIT_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) {
print_verilog_invbuf_module(module_manager, fp, circuit_lib, circuit_model, default_net_type);
print_verilog_invbuf_module(module_manager, fp, circuit_lib, circuit_model, options.default_net_type());
continue;
}
if (CIRCUIT_MODEL_PASSGATE == circuit_lib.model_type(circuit_model)) {
print_verilog_passgate_module(module_manager, fp, circuit_lib, circuit_model, default_net_type);
print_verilog_passgate_module(module_manager, fp, circuit_lib, circuit_model, options.default_net_type());
continue;
}
if (CIRCUIT_MODEL_GATE == circuit_lib.model_type(circuit_model)) {
print_verilog_gate_module(module_manager, fp, circuit_lib, circuit_model, default_net_type);
print_verilog_gate_module(module_manager, fp, circuit_lib, circuit_model, options.default_net_type());
continue;
}
}

3
openfpga/src/fpga_verilog/verilog_essential_gates.h
View File

@ -9,6 +9,7 @@
#include "module_manager.h"
#include "netlist_manager.h"
#include "verilog_port_types.h"
#include "fabric_verilog_options.h"
/********************************************************************
* Function declaration
@ -21,7 +22,7 @@ void print_verilog_submodule_essentials(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const std::string& submodule_dir,
const CircuitLibrary& circuit_lib,
const e_verilog_default_net_type& default_net_type);
const FabricVerilogOption& options);
} /* end namespace openfpga */

2
openfpga/src/fpga_verilog/verilog_formal_random_top_testbench.cpp
View File

@ -291,7 +291,7 @@ void print_verilog_random_top_testbench(const std::string& circuit_name,
/* Generate a brief description on the Verilog file*/
std::string title = std::string("FPGA Verilog Testbench for Formal Top-level netlist of Design: ") + circuit_name;
print_verilog_file_header(fp, title);
print_verilog_file_header(fp, title, options.time_stamp());
/* Preparation: find all the clock ports */
std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);

12
openfpga/src/fpga_verilog/verilog_grid.cpp
View File

@ -95,7 +95,9 @@ void print_verilog_primitive_block(NetlistManager& netlist_manager,
check_file_stream(verilog_fname.c_str(), fp);
print_verilog_file_header(fp, std::string("Verilog modules for primitive pb_type: " + std::string(primitive_pb_graph_node->pb_type->name)));
print_verilog_file_header(fp,
std::string("Verilog modules for primitive pb_type: " + std::string(primitive_pb_graph_node->pb_type->name)),
options.time_stamp());
/* Generate the module name for this primitive pb_graph_node*/
std::string primitive_module_name = generate_physical_block_module_name(primitive_pb_graph_node->pb_type);
@ -207,7 +209,9 @@ void rec_print_verilog_logical_tile(NetlistManager& netlist_manager,
check_file_stream(verilog_fname.c_str(), fp);
print_verilog_file_header(fp, std::string("Verilog modules for pb_type: " + std::string(physical_pb_type->name)));
print_verilog_file_header(fp,
std::string("Verilog modules for pb_type: " + std::string(physical_pb_type->name)),
options.time_stamp());
/* Generate the name of the Verilog module for this pb_type */
std::string pb_module_name = generate_physical_block_module_name(physical_pb_type);
@ -320,7 +324,9 @@ void print_verilog_physical_tile_netlist(NetlistManager& netlist_manager,
check_file_stream(verilog_fname.c_str(), fp);
print_verilog_file_header(fp, std::string("Verilog modules for physical tile: " + std::string(phy_block_type->name) + "]"));
print_verilog_file_header(fp,
std::string("Verilog modules for physical tile: " + std::string(phy_block_type->name) + "]"),
options.time_stamp());
/* Create a Verilog Module for the top-level physical block, and add to module manager */
std::string grid_module_name = generate_grid_block_module_name(std::string(GRID_VERILOG_FILE_NAME_PREFIX), std::string(phy_block_type->name), is_io_type(phy_block_type), border_side);

2
openfpga/src/fpga_verilog/verilog_lut.cpp
View File

@ -47,7 +47,7 @@ void print_verilog_submodule_luts(const ModuleManager& module_manager,
VTR_LOG("Writing Verilog netlist for LUTs '%s'...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Look-Up Tables");
print_verilog_file_header(fp, "Look-Up Tables", options.time_stamp());
/* Search for each LUT circuit model */
for (const auto& lut_model : circuit_lib.models()) {

2
openfpga/src/fpga_verilog/verilog_memory.cpp
View File

@ -116,7 +116,7 @@ void print_verilog_submodule_memories(const ModuleManager& module_manager,
VTR_LOG("Writing Verilog netlist for memories '%s' ...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Memories used in FPGA");
print_verilog_file_header(fp, "Memories used in FPGA", options.time_stamp());
/* Create the memory circuits for the multiplexer */
for (auto mux : mux_lib.muxes()) {

4
openfpga/src/fpga_verilog/verilog_mux.cpp
View File

@ -1274,7 +1274,7 @@ void print_verilog_submodule_mux_primitives(ModuleManager& module_manager,
VTR_LOG("Writing Verilog netlist for Multiplexer primitives '%s' ...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Multiplexer primitives");
print_verilog_file_header(fp, "Multiplexer primitives", options.time_stamp());
/* Record if the branch module has been outputted
* since different sizes of routing multiplexers may share the same branch module
@ -1332,7 +1332,7 @@ void print_verilog_submodule_mux_top_modules(ModuleManager& module_manager,
VTR_LOG("Writing Verilog netlist for Multiplexers '%s' ...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Multiplexers");
print_verilog_file_header(fp, "Multiplexers", options.time_stamp());
/* Generate unique Verilog modules for the multiplexers */
for (auto mux : mux_lib.muxes()) {

2
openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp
View File

@ -436,7 +436,7 @@ int print_verilog_preconfig_top_module(const ModuleManager &module_manager,
/* Generate a brief description on the Verilog file*/
std::string title = std::string("Verilog netlist for pre-configured FPGA fabric by design: ") + circuit_name;
print_verilog_file_header(fp, title);
print_verilog_file_header(fp, title, options.time_stamp());
print_verilog_default_net_type_declaration(fp,
options.default_net_type());

8
openfpga/src/fpga_verilog/verilog_routing.cpp
View File

@ -91,7 +91,9 @@ void print_verilog_routing_connection_box_unique_module(NetlistManager& netlist_
check_file_stream(verilog_fname.c_str(), fp);
print_verilog_file_header(fp, std::string("Verilog modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]"));
print_verilog_file_header(fp,
std::string("Verilog modules for Unique Connection Blocks[" + std::to_string(rr_gsb.get_cb_x(cb_type)) + "]["+ std::to_string(rr_gsb.get_cb_y(cb_type)) + "]"),
options.time_stamp());
/* Create a Verilog Module based on the circuit model, and add to module manager */
ModuleId cb_module = module_manager.find_module(generate_connection_block_module_name(cb_type, gsb_coordinate));
@ -194,7 +196,9 @@ void print_verilog_routing_switch_box_unique_module(NetlistManager& netlist_mana
check_file_stream(verilog_fname.c_str(), fp);
print_verilog_file_header(fp, std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]"));
print_verilog_file_header(fp,
std::string("Verilog modules for Unique Switch Blocks[" + std::to_string(rr_gsb.get_sb_x()) + "]["+ std::to_string(rr_gsb.get_sb_y()) + "]"),
options.time_stamp());
/* Create a Verilog Module based on the circuit model, and add to module manager */
ModuleId sb_module = module_manager.find_module(generate_switch_block_module_name(gsb_coordinate));

2
openfpga/src/fpga_verilog/verilog_shift_register_banks.cpp
View File

@ -51,7 +51,7 @@ void print_verilog_submodule_shift_register_banks(const ModuleManager& module_ma
VTR_LOG("Writing Verilog netlist for shift register banks '%s' ...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Shift register banks used in FPGA");
print_verilog_file_header(fp, "Shift register banks used in FPGA", options.time_stamp());
/* Create the memory circuits for the multiplexer */
for (const ModuleId& sr_module : blwl_sr_banks.bl_bank_unique_modules()) {

10
openfpga/src/fpga_verilog/verilog_submodule.cpp
View File

@ -51,14 +51,14 @@ void print_verilog_submodule(ModuleManager& module_manager,
netlist_manager,
submodule_dir,
circuit_lib,
fpga_verilog_opts.default_net_type());
fpga_verilog_opts);
/* Decoders for architecture */
print_verilog_submodule_arch_decoders(const_cast<const ModuleManager&>(module_manager),
netlist_manager,
decoder_lib,
submodule_dir,
fpga_verilog_opts.default_net_type());
fpga_verilog_opts);
/* Routing multiplexers */
/* NOTE: local decoders generation must go before the MUX generation!!!
@ -68,7 +68,7 @@ void print_verilog_submodule(ModuleManager& module_manager,
netlist_manager,
mux_lib, circuit_lib,
submodule_dir,
fpga_verilog_opts.default_net_type());
fpga_verilog_opts);
print_verilog_submodule_muxes(module_manager, netlist_manager, mux_lib, circuit_lib,
submodule_dir,
fpga_verilog_opts);
@ -84,7 +84,7 @@ void print_verilog_submodule(ModuleManager& module_manager,
print_verilog_submodule_wires(const_cast<const ModuleManager&>(module_manager),
netlist_manager, circuit_lib,
submodule_dir,
fpga_verilog_opts.default_net_type());
fpga_verilog_opts);
/* Memories */
print_verilog_submodule_memories(const_cast<const ModuleManager&>(module_manager),
@ -106,7 +106,7 @@ void print_verilog_submodule(ModuleManager& module_manager,
print_verilog_submodule_templates(const_cast<const ModuleManager&>(module_manager),
circuit_lib,
submodule_dir,
fpga_verilog_opts.default_net_type());
fpga_verilog_opts);
}
/* Create a header file to include all the subckts */

6
openfpga/src/fpga_verilog/verilog_submodule_utils.cpp
View File

@ -174,7 +174,7 @@ void print_one_verilog_template_module(const ModuleManager& module_manager,
void print_verilog_submodule_templates(const ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const std::string& submodule_dir,
const e_verilog_default_net_type& default_net_type) {
const FabricVerilogOption& options) {
std::string verilog_fname(submodule_dir + USER_DEFINED_TEMPLATE_VERILOG_FILE_NAME);
/* Create the file stream */
@ -187,7 +187,7 @@ void print_verilog_submodule_templates(const ModuleManager& module_manager,
VTR_LOG("Creating template for user-defined Verilog modules '%s'...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Template for user-defined Verilog modules");
print_verilog_file_header(fp, "Template for user-defined Verilog modules", options.time_stamp());
/* Output essential models*/
for (const auto& model : circuit_lib.models()) {
@ -203,7 +203,7 @@ void print_verilog_submodule_templates(const ModuleManager& module_manager,
print_one_verilog_template_module(module_manager,
fp,
circuit_lib.model_name(model),
default_net_type);
options.default_net_type());
}
/* close file stream */

3
openfpga/src/fpga_verilog/verilog_submodule_utils.h
View File

@ -9,6 +9,7 @@
#include "module_manager.h"
#include "circuit_library.h"
#include "verilog_port_types.h"
#include "fabric_verilog_options.h"
/********************************************************************
* Function declaration
@ -27,7 +28,7 @@ void add_user_defined_verilog_modules(ModuleManager& module_manager,
void print_verilog_submodule_templates(const ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const std::string& submodule_dir,
const e_verilog_default_net_type& default_net_type);
const FabricVerilogOption& options);
} /* end namespace openfpga */

10
openfpga/src/fpga_verilog/verilog_testbench_options.cpp
View File

@ -25,6 +25,7 @@ VerilogTestbenchOption::VerilogTestbenchOption() {
default_net_type_ = VERILOG_DEFAULT_NET_TYPE_NONE;
embedded_bitstream_hdl_type_ = EMBEDDED_BITSTREAM_HDL_MODELSIM;
time_unit_ = 1E-3;
time_stamp_ = true;
verbose_output_ = false;
}
@ -91,6 +92,10 @@ e_embedded_bitstream_hdl_type VerilogTestbenchOption::embedded_bitstream_hdl_typ
return embedded_bitstream_hdl_type_;
}
bool VerilogTestbenchOption::time_stamp() const {
return time_stamp_;
}
bool VerilogTestbenchOption::verbose_output() const {
return verbose_output_;
}
@ -186,6 +191,11 @@ void VerilogTestbenchOption::set_time_unit(const float& time_unit) {
time_unit_ = time_unit;
}
void VerilogTestbenchOption::set_time_stamp(const bool& enabled) {
time_stamp_ = enabled;
}
void VerilogTestbenchOption::set_verbose_output(const bool& enabled) {
verbose_output_ = enabled;
}

3
openfpga/src/fpga_verilog/verilog_testbench_options.h
View File

@ -47,6 +47,7 @@ class VerilogTestbenchOption {
e_verilog_default_net_type default_net_type() const;
e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type() const;
float time_unit() const;
bool time_stamp() const;
bool verbose_output() const;
public: /* Public validator */
bool validate() const;
@ -73,6 +74,7 @@ class VerilogTestbenchOption {
void set_default_net_type(const std::string& default_net_type);
void set_time_unit(const float& time_unit);
void set_embedded_bitstream_hdl_type(const std::string& embedded_bitstream_hdl_type);
void set_time_stamp(const bool& enabled);
void set_verbose_output(const bool& enabled);
private: /* Internal Data */
std::string output_directory_;
@ -89,6 +91,7 @@ class VerilogTestbenchOption {
e_verilog_default_net_type default_net_type_;
e_embedded_bitstream_hdl_type embedded_bitstream_hdl_type_;
float time_unit_;
bool time_stamp_;
bool verbose_output_;
};

4
openfpga/src/fpga_verilog/verilog_top_module.cpp
View File

@ -56,7 +56,9 @@ void print_verilog_top_module(NetlistManager& netlist_manager,
check_file_stream(verilog_fname.c_str(), fp);
print_verilog_file_header(fp, std::string("Top-level Verilog module for FPGA"));
print_verilog_file_header(fp,
std::string("Top-level Verilog module for FPGA"),
options.time_stamp());
/* Write the module content in Verilog format */
write_verilog_module_to_file(fp,

2
openfpga/src/fpga_verilog/verilog_top_testbench.cpp
View File

@ -1928,7 +1928,7 @@ int print_verilog_full_testbench(const ModuleManager& module_manager,
/* Generate a brief description on the Verilog file*/
std::string title = std::string("FPGA Verilog full testbench for top-level netlist of design: ") + circuit_name;
print_verilog_file_header(fp, title);
print_verilog_file_header(fp, title, options.time_stamp());
/* Find the top_module */
ModuleId top_module = module_manager.find_module(generate_fpga_top_module_name());

6
openfpga/src/fpga_verilog/verilog_wire.cpp
View File

@ -97,7 +97,7 @@ void print_verilog_submodule_wires(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const CircuitLibrary& circuit_lib,
const std::string& submodule_dir,
const e_verilog_default_net_type& default_net_type) {
const FabricVerilogOption& options) {
std::string verilog_fname(submodule_dir + std::string(WIRES_VERILOG_FILE_NAME));
/* Create the file stream */
@ -110,7 +110,7 @@ void print_verilog_submodule_wires(const ModuleManager& module_manager,
VTR_LOG("Writing Verilog netlist for wires '%s'...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Wires");
print_verilog_file_header(fp, "Wires", options.time_stamp());
/* Print Verilog models for regular wires*/
print_verilog_comment(fp, std::string("----- BEGIN Verilog modules for regular wires -----"));
@ -119,7 +119,7 @@ void print_verilog_submodule_wires(const ModuleManager& module_manager,
if (!circuit_lib.model_verilog_netlist(model).empty()) {
continue;
}
print_verilog_wire_module(module_manager, circuit_lib, fp, model, default_net_type);
print_verilog_wire_module(module_manager, circuit_lib, fp, model, options.default_net_type());
}
print_verilog_comment(fp, std::string("----- END Verilog modules for regular wires -----"));

3
openfpga/src/fpga_verilog/verilog_wire.h
View File

@ -11,6 +11,7 @@
#include "module_manager.h"
#include "netlist_manager.h"
#include "verilog_port_types.h"
#include "fabric_verilog_options.h"
/********************************************************************
* Function declaration
@ -23,7 +24,7 @@ void print_verilog_submodule_wires(const ModuleManager& module_manager,
NetlistManager& netlist_manager,
const CircuitLibrary& circuit_lib,
const std::string& submodule_dir,
const e_verilog_default_net_type& default_net_type);
const FabricVerilogOption& options);
} /* end namespace openfpga */

18
openfpga/src/fpga_verilog/verilog_writer_utils.cpp
View File

@ -43,19 +43,24 @@ void print_verilog_default_net_type_declaration(std::fstream& fp,
* include the description
***********************************************/
void print_verilog_file_header(std::fstream& fp,
const std::string& usage) {
const std::string& usage,
const bool& include_time_stamp) {
VTR_ASSERT(true == valid_file_stream(fp));
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "//-------------------------------------------" << std::endl;
fp << "//\tFPGA Synthesizable Verilog Netlist" << std::endl;
fp << "//\tDescription: " << usage << std::endl;
fp << "//\tAuthor: Xifan TANG" << std::endl;
fp << "//\tOrganization: University of Utah" << std::endl;
if (include_time_stamp) {
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
fp << "//\tDate: " << std::ctime(&end_time) ;
}
fp << "//-------------------------------------------" << std::endl;
fp << "//----- Time scale -----" << std::endl;
fp << "`timescale 1ns / 1ps" << std::endl;
fp << std::endl;
@ -1531,7 +1536,8 @@ void print_verilog_clock_stimuli(std::fstream& fp,
********************************************************************/
void print_verilog_netlist_include_header_file(const std::vector<std::string>& netlists_to_be_included,
const char* subckt_dir,
const char* header_file_name) {
const char* header_file_name,
const bool& include_time_stamp) {
std::string verilog_fname(std::string(subckt_dir) + std::string(header_file_name));
@ -1542,7 +1548,7 @@ void print_verilog_netlist_include_header_file(const std::vector<std::string>& n
VTR_ASSERT(true == valid_file_stream(fp));
/* Generate the descriptions*/
print_verilog_file_header(fp, "Header file to include other Verilog netlists");
print_verilog_file_header(fp, "Header file to include other Verilog netlists", include_time_stamp);
/* Output file names */
for (const std::string& netlist_name : netlists_to_be_included) {

6
openfpga/src/fpga_verilog/verilog_writer_utils.h
View File

@ -35,7 +35,8 @@ void print_verilog_default_net_type_declaration(std::fstream& fp,
const e_verilog_default_net_type& default_net_type);
void print_verilog_file_header(std::fstream& fp,
const std::string& usage);
const std::string& usage,
const bool& include_time_stamp);
void print_verilog_include_netlist(std::fstream& fp,
const std::string& netlist_name);
@ -201,7 +202,8 @@ void print_verilog_clock_stimuli(std::fstream& fp,
void print_verilog_netlist_include_header_file(const std::vector<std::string>& netlists_to_be_included,
const char* subckt_dir,
const char* header_file_name);
const char* header_file_name,
const bool& include_time_stamp);
} /* end namespace openfpga */