Merge pull request #92 from LNIS-Projects/dev

Smart Configuration Support and Verilog Netlist Refactoring

.travis/basic_reg_test.sh

@@ -12,23 +12,49 @@ echo -e "Basic regression tests";
 
 echo -e "Testing configuration chain of a K4N4 FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs
 
 echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs
 
 echo -e "Testing memory bank configuration protocol of a K4N4 FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs
 
 echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/flatten_memory --debug --show_thread_logs
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs
 
+echo -e "Testing fixed device layout and routing channel width";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_device_support --debug --show_thread_logs
+
 echo -e "Testing fabric Verilog generation only";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --debug --show_thread_logs
 
@@ -51,5 +77,7 @@ echo -e "Testing K4N4 with multiple lengths of routing segments";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs
 echo -e "Testing K4N4 with 32-bit fracturable multiplier";
 python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs
+echo -e "Testing K4N5 with pattern based local routing";
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs
 
 end_section "OpenFPGA.TaskTun"

docs/source/manual/arch_lang/circuit_library.rst

@@ -143,7 +143,8 @@ A circuit model may consist of a number of ports. The port list is mandatory in
 
 .. option:: <port type="<string>" prefix="<string>" lib_name="<string>" size="<int>"
   default_val="<int>" circuit_model_name="<string>" mode_select="<bool>"
-  is_global="<bool>" is_set="<bool>" is_reset="<bool>" is_config_enable="<bool>"/>
+  is_global="<bool>" is_set="<bool>" is_reset="<bool>" 
+  is_edge_triggered="<bool>" is_config_enable="<bool>"/>
 
   Define the attributes for a port of a circuit model.
 
@@ -190,6 +191,8 @@ A circuit model may consist of a number of ports. The port list is mandatory in
 
   - ``is_config_enable="true|false"`` Specify if this port controls a configuration-enable signal. Only valid when ``is_global`` is ``true``. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches.
 
+  - ``is_edge_triggered="true|false"`` Specify if this port is edge sensitive, like the clock port of a D-type flip-flop. This attribute is used to create stimuli in testbenches when flip-flops are used as configurable memory in frame-based configuration protocol.
+
 .. note:: ``is_set``, ``is_reset`` and ``is_config_enable`` are only valid when ``is_global`` is ``true``. 
 
 .. note::  Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of :ref:``circuit_model_example`` for more details.

docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst

@@ -33,6 +33,8 @@ write_verilog_testbench
 
   - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. 
 
+    .. note:: If both reset and set ports are defined in the circuit modeling for programming, OpenFPGA will pick the one that will bring largest benefit in speeding up configuration.
+
   - ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 
   - ``--print_formal_verification_top_netlist`` Generate a top-level module which can be used in formal verification

libopenfpga/libarchopenfpga/src/circuit_library.cpp

@@ -942,6 +942,12 @@ bool CircuitLibrary::port_is_config_enable(const CircuitPortId& circuit_port_id)
   return port_is_config_enable_[circuit_port_id];
 }
 
+bool CircuitLibrary::port_is_edge_triggered(const CircuitPortId& circuit_port_id) const {
+  /* validate the circuit_port_id */
+  VTR_ASSERT(valid_circuit_port_id(circuit_port_id));
+  return port_is_edge_triggered_[circuit_port_id];
+}
+
 /* Return a flag if the port is used during programming a FPGA in a circuit model */
 bool CircuitLibrary::port_is_prog(const CircuitPortId& circuit_port_id) const {
   /* validate the circuit_port_id */
@@ -1374,6 +1380,7 @@ CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id,
   port_is_reset_.push_back(false);
   port_is_set_.push_back(false);
   port_is_config_enable_.push_back(false);
+  port_is_edge_triggered_.push_back(false);
   port_is_prog_.push_back(false);
   port_tri_state_model_names_.emplace_back();
   port_tri_state_model_ids_.push_back(CircuitModelId::INVALID());
@@ -1493,6 +1500,15 @@ void CircuitLibrary::set_port_is_config_enable(const CircuitPortId& circuit_port
   return;
 }
 
+/* Set the is_edge_triggered for a port of a circuit model */
+void CircuitLibrary::set_port_is_edge_triggered(const CircuitPortId& circuit_port_id, 
+                                                const bool& is_edge_triggered) {
+  /* validate the circuit_port_id */
+  VTR_ASSERT(valid_circuit_port_id(circuit_port_id));
+  port_is_edge_triggered_[circuit_port_id] = is_edge_triggered;
+  return;
+}
+
 /* Set the is_prog for a port of a circuit model */
 void CircuitLibrary::set_port_is_prog(const CircuitPortId& circuit_port_id, 
                                       const bool& is_prog) {

libopenfpga/libarchopenfpga/src/circuit_library.h

@@ -91,15 +91,16 @@
  * 9. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches 
  * 10. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches 
  * 11. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches 
- * 12. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches 
- * 13. port_tri_state_model_name: the name of circuit model linked to tri-state the port  
- * 14. port_tri_state_model_ids_: the Id of circuit model linked to tri-state the port 
- * 15. port_inv_model_names_: the name of inverter circuit model linked to the port 
- * 16. port_inv_model_ids_: the Id of inverter circuit model linked to the port
- * 17. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port 
- * 18. port_lut_frac_level_:  only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used
- * 19. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used
- * 20. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains
+ * 12. port_is_edge_triggered: specify if this port is triggerd by edges like the clock signal of a D-type flip-flop 
+ * 13. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches 
+ * 14. port_tri_state_model_name: the name of circuit model linked to tri-state the port  
+ * 15. port_tri_state_model_ids_: the Id of circuit model linked to tri-state the port 
+ * 16. port_inv_model_names_: the name of inverter circuit model linked to the port 
+ * 17. port_inv_model_ids_: the Id of inverter circuit model linked to the port
+ * 18. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port 
+ * 19. port_lut_frac_level_:  only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used
+ * 20. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used
+ * 21. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains
  *
  *  ------ Delay information ------
  * 1. delay_types_: type of pin-to-pin delay, either rising_edge of falling_edge
@@ -284,6 +285,7 @@ class CircuitLibrary {
     bool port_is_reset(const CircuitPortId& circuit_port_id) const;
     bool port_is_set(const CircuitPortId& circuit_port_id) const;
     bool port_is_config_enable(const CircuitPortId& circuit_port_id) const;
+    bool port_is_edge_triggered(const CircuitPortId& circuit_port_id) const;
     bool port_is_prog(const CircuitPortId& circuit_port_id) const;
     size_t port_lut_frac_level(const CircuitPortId& circuit_port_id) const;
     std::vector<size_t> port_lut_output_mask(const CircuitPortId& circuit_port_id) const;
@@ -364,6 +366,8 @@ class CircuitLibrary {
                          const bool& is_set);
     void set_port_is_config_enable(const CircuitPortId& circuit_port_id, 
                                    const bool& is_config_enable);
+    void set_port_is_edge_triggered(const CircuitPortId& circuit_port_id, 
+                                    const bool& is_edge_triggered);
     void set_port_is_prog(const CircuitPortId& circuit_port_id, 
                           const bool& is_prog);
     void set_port_tri_state_model_name(const CircuitPortId& circuit_port_id, 
@@ -550,6 +554,7 @@ class CircuitLibrary {
     vtr::vector<CircuitPortId, bool> port_is_reset_;
     vtr::vector<CircuitPortId, bool> port_is_set_;
     vtr::vector<CircuitPortId, bool> port_is_config_enable_;
+    vtr::vector<CircuitPortId, bool> port_is_edge_triggered_;
     vtr::vector<CircuitPortId, bool> port_is_prog_;
     vtr::vector<CircuitPortId, std::string> port_tri_state_model_names_;
     vtr::vector<CircuitPortId, CircuitModelId> port_tri_state_model_ids_;

libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp

@@ -564,6 +564,9 @@ void read_xml_circuit_port(pugi::xml_node& xml_port,
   /* Identify if the port is to enable programming for FPGAs, by default it is NOT */
   circuit_lib.set_port_is_config_enable(port, get_attribute(xml_port, "is_config_enable", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
 
+  /* Identify if the port is to triggered by edges, by default it is NOT */
+  circuit_lib.set_port_is_edge_triggered(port, get_attribute(xml_port, "is_edge_triggered", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false));
+
   /* Find the name of circuit model that this port is linked to */
   circuit_lib.set_port_tri_state_model_name(port, get_attribute(xml_port, "circuit_model_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string());
 

libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp

@@ -207,6 +207,10 @@ void write_xml_circuit_port(std::fstream& fp,
     write_xml_attribute(fp, "is_config_enable", "true"); 
   }
 
+  if (true == circuit_lib.port_is_edge_triggered(port)) {
+    write_xml_attribute(fp, "is_edge_triggered", "true"); 
+  }
+
   /* Output the name of circuit model that this port is linked to */
   if (!circuit_lib.port_tri_state_model_name(port).empty()) {
     write_xml_attribute(fp, "circuit_model_name", circuit_lib.port_tri_state_model_name(port).c_str());

openfpga/src/base/openfpga_verilog.cpp

@@ -97,7 +97,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx,
                          openfpga_ctx.vpr_netlist_annotation(),
                          openfpga_ctx.arch().circuit_lib,
                          openfpga_ctx.simulation_setting(),
-                         openfpga_ctx.arch().config_protocol.type(),
+                         openfpga_ctx.arch().config_protocol,
                          options);
 
   /* TODO: should identify the error code from internal function execution */

openfpga/src/fabric/build_memory_modules.cpp

@@ -636,13 +636,13 @@ void build_frame_memory_module(ModuleManager& module_manager,
     module_manager.add_configurable_child(mem_module, sram_mem_module, sram_instance);
 
     /* Wire data_in port to SRAM BL port */
-    ModulePortId sram_bl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_lib_name(sram_bl_ports[0]));
+    ModulePortId sram_bl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_prefix(sram_bl_ports[0]));
     add_module_bus_nets(module_manager, mem_module,
                         mem_module, 0, mem_data_port,
                         sram_mem_module, sram_instance, sram_bl_port);
 
     /* Wire decoder data_out port to sram WL ports */
-    ModulePortId sram_wl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_lib_name(sram_wl_ports[0]));
+    ModulePortId sram_wl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_prefix(sram_wl_ports[0]));
     ModulePortId decoder_data_port = module_manager.find_module_port(decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME));
     ModuleNetId wl_net = module_manager.create_module_net(mem_module);
     /* Source node of the input net is the input of memory module */

openfpga/src/fpga_verilog/verilog_api.cpp

@@ -156,7 +156,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager,
                             const VprNetlistAnnotation &netlist_annotation,
                             const CircuitLibrary &circuit_lib,
                             const SimulationSetting &simulation_setting,
-                            const e_config_protocol_type &config_protocol_type,
+                            const ConfigProtocol &config_protocol,
                             const VerilogTestbenchOption &options) {
 
   vtr::ScopedStartFinishTimer timer("Write Verilog testbenches for FPGA fabric\n");
@@ -205,7 +205,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager,
     std::string top_testbench_file_path = src_dir_path + netlist_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX);
     print_verilog_top_testbench(module_manager,
                                 bitstream_manager, fabric_bitstream,
-                                config_protocol_type,
+                                config_protocol,
                                 circuit_lib, global_ports,
                                 atom_ctx, place_ctx, io_location_map,
                                 netlist_annotation,
@@ -225,7 +225,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager,
                                   src_dir_path,
                                   atom_ctx, place_ctx, io_location_map,
                                   module_manager,
-                                  config_protocol_type,
+                                  config_protocol.type(),
                                   bitstream_manager.num_bits(),
                                   simulation_setting.num_clock_cycles(),
                                   simulation_setting.programming_clock_frequency(),

openfpga/src/fpga_verilog/verilog_api.h

@@ -10,6 +10,7 @@
 #include "mux_library.h"
 #include "decoder_library.h"
 #include "circuit_library.h"
+#include "config_protocol.h"
 #include "vpr_context.h"
 #include "vpr_device_annotation.h"
 #include "device_rr_gsb.h"
@@ -49,7 +50,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager,
                             const VprNetlistAnnotation& netlist_annotation, 
                             const CircuitLibrary& circuit_lib,
                             const SimulationSetting& simulation_parameters,
-                            const e_config_protocol_type& config_protocol_type,
+                            const ConfigProtocol& config_protocol,
                             const VerilogTestbenchOption& options);
 
 

openfpga/src/fpga_verilog/verilog_top_testbench.cpp

@@ -60,6 +60,54 @@ constexpr char* TOP_TB_CLOCK_REG_POSTFIX = "_reg";
 
 constexpr char* AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX = "_autocheck_top_tb";
 
+/********************************************************************
+ * Identify global reset ports for programming 
+ *******************************************************************/
+static 
+std::vector<CircuitPortId> find_global_programming_reset_ports(const CircuitLibrary& circuit_lib,
+                                                               const std::vector<CircuitPortId>& global_ports) {
+  /* Try to find global reset ports for programming */
+  std::vector<CircuitPortId> global_prog_reset_ports;
+  for (const CircuitPortId& global_port : global_ports) {
+    VTR_ASSERT(true == circuit_lib.port_is_global(global_port));
+    if (false == circuit_lib.port_is_prog(global_port)) {
+      continue;
+    }
+    VTR_ASSERT(true == circuit_lib.port_is_prog(global_port));
+    VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port))
+               || (false == circuit_lib.port_is_set(global_port)));
+    if (true == circuit_lib.port_is_reset(global_port)) {
+      global_prog_reset_ports.push_back(global_port);
+    }
+  }
+
+  return global_prog_reset_ports;
+}
+
+/********************************************************************
+ * Identify global set ports for programming 
+ *******************************************************************/
+static 
+std::vector<CircuitPortId> find_global_programming_set_ports(const CircuitLibrary& circuit_lib,
+                                                             const std::vector<CircuitPortId>& global_ports) {
+  /* Try to find global set ports for programming */
+  std::vector<CircuitPortId> global_prog_set_ports;
+  for (const CircuitPortId& global_port : global_ports) {
+    VTR_ASSERT(true == circuit_lib.port_is_global(global_port));
+    if (false == circuit_lib.port_is_prog(global_port)) {
+      continue;
+    }
+    VTR_ASSERT(true == circuit_lib.port_is_prog(global_port));
+    VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port))
+               || (false == circuit_lib.port_is_set(global_port)));
+    if (true == circuit_lib.port_is_set(global_port)) {
+      global_prog_set_ports.push_back(global_port);
+    }
+  }
+
+  return global_prog_set_ports;
+}
+
 /********************************************************************
  * Print local wires for flatten memory (standalone) configuration protocols
  *******************************************************************/
@@ -136,15 +184,15 @@ void print_verilog_top_testbench_memory_bank_port(std::fstream& fp,
   BasicPort din_port = module_manager.module_port(top_module, din_port_id);
   fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl;
 
-  /* Wire the INVERTED programming clock to the enable signal !!! */
-  print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock -----"));
+  /* Wire the INVERTED configuration done signal to the enable signal !!! */
+  print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----"));
   ModulePortId en_port_id = module_manager.find_module_port(top_module,
                                                             std::string(DECODER_ENABLE_PORT_NAME));
   BasicPort en_port = module_manager.module_port(top_module, en_port_id);
-  BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
+  BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1);
 
   fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl;
-  print_verilog_wire_connection(fp, en_port, prog_clock_port, true);
+  print_verilog_wire_connection(fp, en_port, config_done_port, true);
 }
 
 
@@ -153,6 +201,8 @@ void print_verilog_top_testbench_memory_bank_port(std::fstream& fp,
  *******************************************************************/
 static
 void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp,
+                                                    const ConfigProtocol& config_protocol,
+                                                    const CircuitLibrary& circuit_lib,
                                                     const ModuleManager& module_manager,
                                                     const ModuleId& top_module) {
   /* Validate the file stream */
@@ -173,15 +223,33 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp,
   BasicPort din_port = module_manager.module_port(top_module, din_port_id);
   fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl;
 
-  /* Wire the INVERTED programming clock to the enable signal !!! */
-  print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock -----"));
+  /* Wire the INVERTED configuration done signal to the enable signal !!! */
   ModulePortId en_port_id = module_manager.find_module_port(top_module,
                                                             std::string(DECODER_ENABLE_PORT_NAME));
   BasicPort en_port = module_manager.module_port(top_module, en_port_id);
-  BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
 
+  /* Find the circuit model of configurable memory
+   * Spot its BL port and generate stimuli based on BL port's attribute:
+   * - If the BL port is triggered by edge, use the inverted programming clock signal
+   * - If the BL port is a regular port, use the inverted configuration done signal
+   */
+  const CircuitModelId& mem_model = config_protocol.memory_model();
+  VTR_ASSERT(true == circuit_lib.valid_model_id(mem_model));
+  std::vector<CircuitPortId> mem_model_bl_ports = circuit_lib.model_ports_by_type(mem_model, CIRCUIT_MODEL_PORT_BL);
+  VTR_ASSERT(1 == mem_model_bl_ports.size());
+
+  if (true == circuit_lib.port_is_edge_triggered(mem_model_bl_ports[0])) {
+    VTR_ASSERT_SAFE(false == circuit_lib.port_is_edge_triggered(mem_model_bl_ports[0]));
+    BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1);
+    print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock signal -----"));
     fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl;
     print_verilog_wire_connection(fp, en_port, prog_clock_port, true);
+  } else {
+    BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1);
+    print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----"));
+    fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl;
+    print_verilog_wire_connection(fp, en_port, config_done_port, true);
+  }
 }
 
 /********************************************************************
@@ -189,10 +257,11 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp,
  *******************************************************************/
 static
 void print_verilog_top_testbench_config_protocol_port(std::fstream& fp,
-                                                      const e_config_protocol_type& sram_orgz_type,
+                                                      const ConfigProtocol& config_protocol,
+                                                      const CircuitLibrary& circuit_lib,
                                                       const ModuleManager& module_manager,
                                                       const ModuleId& top_module) {
-  switch(sram_orgz_type) {
+  switch(config_protocol.type()) {
   case CONFIG_MEM_STANDALONE:
     print_verilog_top_testbench_flatten_memory_port(fp, module_manager, top_module);
     break;
@@ -203,7 +272,8 @@ void print_verilog_top_testbench_config_protocol_port(std::fstream& fp,
     print_verilog_top_testbench_memory_bank_port(fp, module_manager, top_module);
     break;
   case CONFIG_MEM_FRAME_BASED:
-    print_verilog_top_testbench_frame_decoder_port(fp, module_manager, top_module);
+    print_verilog_top_testbench_frame_decoder_port(fp, config_protocol, circuit_lib,
+                                                   module_manager, top_module);
     break;
   default:
     VTR_LOGF_ERROR(__FILE__, __LINE__,
@@ -220,7 +290,9 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
                                                       const ModuleManager& module_manager,
                                                       const ModuleId& top_module,
                                                       const CircuitLibrary& circuit_lib,
-                                                      const std::vector<CircuitPortId>& global_ports) {
+                                                      const std::vector<CircuitPortId>& global_ports,
+                                                      const bool& active_global_prog_reset,
+                                                      const bool& active_global_prog_set) {
   /* Validate the file stream */
   valid_file_stream(fp);
 
@@ -302,10 +374,13 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
     ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port));
     VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port));
 
+    /* For global programming reset port, we will active only when specified */
     BasicPort stimuli_reset_port;
+    bool activate = true;
     if (true == circuit_lib.port_is_prog(model_global_port)) {
       stimuli_reset_port.set_name(std::string(TOP_TB_PROG_RESET_PORT_NAME));
       stimuli_reset_port.set_width(1);
+      activate = active_global_prog_reset;
     } else {
       VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port));
       stimuli_reset_port.set_name(std::string(TOP_TB_RESET_PORT_NAME));
@@ -315,9 +390,15 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
      * The wiring will be inverted if the default value of the global port is 1
      * Otherwise, the wiring will not be inverted!
      */
+    if (true == activate) {
       print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port),
                                     stimuli_reset_port,
                                     1 == circuit_lib.port_default_value(model_global_port));
+    } else {
+      VTR_ASSERT_SAFE(false == activate);
+      print_verilog_wire_constant_values(fp, module_manager.module_port(top_module, module_global_port),
+                                         std::vector<size_t>(1, circuit_lib.port_default_value(model_global_port)));
+    }
   }
 
   /* Connect global set ports to operating or programming set signal */
@@ -344,10 +425,13 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
     ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port));
     VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port));
 
+    /* For global programming set port, we will active only when specified */
     BasicPort stimuli_set_port;
+    bool activate = true;
     if (true == circuit_lib.port_is_prog(model_global_port)) {
       stimuli_set_port.set_name(std::string(TOP_TB_PROG_SET_PORT_NAME));
       stimuli_set_port.set_width(1);
+      activate = active_global_prog_set;
     } else {
       VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port));
       stimuli_set_port.set_name(std::string(TOP_TB_SET_PORT_NAME));
@@ -357,9 +441,15 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp,
      * The wiring will be inverted if the default value of the global port is 1
      * Otherwise, the wiring will not be inverted!
      */
+    if (true == activate) {
       print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port),
                                     stimuli_set_port,
                                     1 == circuit_lib.port_default_value(model_global_port));
+    } else {
+      VTR_ASSERT_SAFE(false == activate);
+      print_verilog_wire_constant_values(fp, module_manager.module_port(top_module, module_global_port),
+                                         std::vector<size_t>(1, circuit_lib.port_default_value(model_global_port)));
+    }
   }
 
   /* For the rest of global ports, wire them to constant signals */
@@ -434,7 +524,8 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
                                        const AtomContext& atom_ctx,
                                        const VprNetlistAnnotation& netlist_annotation,
                                        const std::vector<std::string>& clock_port_names,
-                                       const e_config_protocol_type& sram_orgz_type,
+                                       const ConfigProtocol& config_protocol,
+                                       const CircuitLibrary& circuit_lib,
                                        const std::string& circuit_name){
   /* Validate the file stream */
   valid_file_stream(fp);
@@ -508,7 +599,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
   fp << generate_verilog_port(VERILOG_PORT_REG, set_port) << ";" << std::endl;
 
   /* Configuration ports depend on the organization of SRAMs */
-  print_verilog_top_testbench_config_protocol_port(fp, sram_orgz_type,
+  print_verilog_top_testbench_config_protocol_port(fp, config_protocol, circuit_lib,
                                                    module_manager, top_module);
 
   /* Create a clock port if the benchmark have one but not in the default name!
@@ -561,6 +652,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp,
 static
 size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz_type,
                                          const bool& fast_configuration,
+                                         const bool& bit_value_to_skip,
                                          const BitstreamManager& bitstream_manager,
                                          const FabricBitstream& fabric_bitstream) {
   size_t num_config_clock_cycles = 1 + fabric_bitstream.num_bits();
@@ -579,7 +671,7 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz
       size_t full_num_config_clock_cycles = num_config_clock_cycles;
       size_t num_bits_to_skip = 0;
       for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
-        if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) {
+        if (bit_value_to_skip != bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) {
           break;
         }
         num_bits_to_skip++;
@@ -600,7 +692,7 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz
       size_t full_num_config_clock_cycles = num_config_clock_cycles;
       num_config_clock_cycles = 1;
       for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
-        if (true == fabric_bitstream.bit_din(bit_id)) {
+        if (bit_value_to_skip != fabric_bitstream.bit_din(bit_id)) {
           num_config_clock_cycles++;
         }
       }
@@ -985,11 +1077,11 @@ void print_verilog_top_testbench_generic_stimulus(std::fstream& fp,
   fp << std::endl;
 
   /* Programming set signal for configuration circuit : always disabled */
-  print_verilog_comment(fp, "----- Begin programming set signal generation: always disabled -----");
+  print_verilog_comment(fp, "----- Begin programming set signal generation -----");
   print_verilog_pulse_stimuli(fp, prog_set_port,
-                              0, /* Initial value */
+                              1, /* Initial value */
                               prog_clock_period / timescale, 0);
-  print_verilog_comment(fp, "----- End programming set signal generation: always disabled -----");
+  print_verilog_comment(fp, "----- End programming set signal generation -----");
 
   fp << std::endl;
 
@@ -1112,6 +1204,102 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp,
   print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----");
 }
 
+/********************************************************************
+ * Decide if we should use reset or set signal to acheive fast configuration
+ * - If only one type signal is specified, we use that type
+ *   For example, only reset signal is defined, we will use reset  
+ * - If both are defined, pick the one that will bring bigger reduction
+ *   i.e., larger number of configuration bits can be skipped
+ *******************************************************************/
+static 
+bool find_bit_value_to_skip_for_fast_configuration(const e_config_protocol_type& config_protocol_type,  
+                                                   const bool& fast_configuration,
+                                                   const std::vector<CircuitPortId>& global_prog_reset_ports,
+                                                   const std::vector<CircuitPortId>& global_prog_set_ports,
+                                                   const BitstreamManager& bitstream_manager,
+                                                   const FabricBitstream& fabric_bitstream) {
+
+  /* Early exit conditions */
+  if (!global_prog_reset_ports.empty() && global_prog_set_ports.empty()) {
+    return false; 
+  } else if (!global_prog_set_ports.empty() && global_prog_reset_ports.empty()) {
+    return true; 
+  } else if (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) {
+    /* If both types of ports are not defined, the fast configuration should be turned off */
+    VTR_ASSERT(false == fast_configuration); 
+    return false;
+  }
+
+  VTR_ASSERT(!global_prog_set_ports.empty() && !global_prog_reset_ports.empty());
+  bool bit_value_to_skip = false;
+
+  VTR_LOG("Both reset and set ports are defined for programming controls, selecting the best-fit one...\n");
+
+  size_t num_ones_to_skip = 0;
+  size_t num_zeros_to_skip = 0;
+
+  /* Branch on the type of configuration protocol */
+  switch (config_protocol_type) {
+  case CONFIG_MEM_STANDALONE:
+    break;
+  case CONFIG_MEM_SCAN_CHAIN: {
+    /* We can only skip the ones/zeros at the beginning of the bitstream */
+    /* Count how many logic '1' bits we can skip */
+    for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
+      if (false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) {
+        break;
+      }
+      VTR_ASSERT(true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)));
+      num_ones_to_skip++;
+    }
+    /* Count how many logic '0' bits we can skip */
+    for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
+      if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) {
+        break;
+      }
+      VTR_ASSERT(false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)));
+      num_zeros_to_skip++;
+    }
+    break;
+  }
+  case CONFIG_MEM_MEMORY_BANK:
+  case CONFIG_MEM_FRAME_BASED: {
+    /* Count how many logic '1' and logic '0' bits we can skip */
+    for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
+      if (false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) {
+        num_zeros_to_skip++;
+      } else {
+        VTR_ASSERT(true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)));
+        num_ones_to_skip++;
+      }
+    }
+    break;
+  }
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid SRAM organization type!\n");
+    exit(1);
+  }
+
+  VTR_LOG("Using reset will skip %g% (%lu/%lu) of configuration bitstream.\n",
+          100. * (float) num_zeros_to_skip / (float) fabric_bitstream.num_bits(),
+          num_zeros_to_skip, fabric_bitstream.num_bits());
+
+  VTR_LOG("Using set will skip %g% (%lu/%lu) of configuration bitstream.\n",
+          100. * (float) num_ones_to_skip / (float) fabric_bitstream.num_bits(),
+          num_ones_to_skip, fabric_bitstream.num_bits());
+
+  /* By default, we prefer to skip zeros (when the numbers are the same */
+  if (num_ones_to_skip > num_zeros_to_skip) {
+    VTR_LOG("Will use set signal in fast configuration\n");
+    bit_value_to_skip = true;
+  } else {
+    VTR_LOG("Will use reset signal in fast configuration\n");
+  }
+
+  return bit_value_to_skip;
+}
+
 /********************************************************************
  * Print stimulus for a FPGA fabric with a configuration chain protocol
  * where configuration bits are programming in serial (one by one)
@@ -1127,6 +1315,7 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp,
 static
 void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
                                                                const bool& fast_configuration,
+                                                               const bool& bit_value_to_skip,
                                                                const BitstreamManager& bitstream_manager,
                                                                const FabricBitstream& fabric_bitstream) {
   /* Validate the file stream */
@@ -1151,13 +1340,14 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
 
   fp << std::endl;
 
+
   /* Attention: when the fast configuration is enabled, we will start from the first bit '1'
    * This requires a reset signal (as we forced in the first clock cycle)
    */
   bool start_config = false;
   for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
     if ( (false == start_config)
-      && (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)))) {
+      && (bit_value_to_skip != bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)))) {
       start_config = true;
     } 
 
@@ -1198,6 +1388,7 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp,
 static
 void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp,
                                                        const bool& fast_configuration,
+                                                       const bool& bit_value_to_skip,
                                                        const ModuleManager& module_manager,
                                                        const ModuleId& top_module,
                                                        const FabricBitstream& fabric_bitstream) {
@@ -1249,7 +1440,7 @@ void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp,
   for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
     /* When fast configuration is enabled, we skip zero data_in values */
     if ((true == fast_configuration)
-      && (false == fabric_bitstream.bit_din(bit_id))) {
+      && (bit_value_to_skip == fabric_bitstream.bit_din(bit_id))) {
       continue;
     }
 
@@ -1303,6 +1494,7 @@ void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp,
 static
 void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp,
                                                          const bool& fast_configuration,
+                                                         const bool& bit_value_to_skip,
                                                          const ModuleManager& module_manager,
                                                          const ModuleId& top_module,
                                                          const FabricBitstream& fabric_bitstream) {
@@ -1345,7 +1537,7 @@ void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp,
   for (const FabricBitId& bit_id : fabric_bitstream.bits()) {
     /* When fast configuration is enabled, we skip zero data_in values */
     if ((true == fast_configuration)
-      && (false == fabric_bitstream.bit_din(bit_id))) {
+      && (bit_value_to_skip == fabric_bitstream.bit_din(bit_id))) {
       continue;
     }
 
@@ -1401,14 +1593,16 @@ void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp,
  *******************************************************************/
 static
 void print_verilog_top_testbench_bitstream(std::fstream& fp,
-                                           const e_config_protocol_type& sram_orgz_type,
+                                           const e_config_protocol_type& config_protocol_type,
                                            const bool& fast_configuration,
+                                           const bool& bit_value_to_skip,
                                            const ModuleManager& module_manager,
                                            const ModuleId& top_module,
                                            const BitstreamManager& bitstream_manager,
                                            const FabricBitstream& fabric_bitstream) {
+
   /* Branch on the type of configuration protocol */
-  switch (sram_orgz_type) {
+  switch (config_protocol_type) {
   case CONFIG_MEM_STANDALONE:
     print_verilog_top_testbench_vanilla_bitstream(fp,
                                                   module_manager, top_module,
@@ -1416,15 +1610,18 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp,
     break;
   case CONFIG_MEM_SCAN_CHAIN:
     print_verilog_top_testbench_configuration_chain_bitstream(fp, fast_configuration, 
+                                                              bit_value_to_skip,
                                                               bitstream_manager, fabric_bitstream);
     break;
   case CONFIG_MEM_MEMORY_BANK:
     print_verilog_top_testbench_memory_bank_bitstream(fp, fast_configuration,
+                                                      bit_value_to_skip,
                                                       module_manager, top_module,
                                                       fabric_bitstream);
     break;
   case CONFIG_MEM_FRAME_BASED:
     print_verilog_top_testbench_frame_decoder_bitstream(fp, fast_configuration,
+                                                        bit_value_to_skip,
                                                         module_manager, top_module,
                                                         fabric_bitstream);
     break;
@@ -1458,7 +1655,7 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp,
 void print_verilog_top_testbench(const ModuleManager& module_manager,
                                  const BitstreamManager& bitstream_manager,
                                  const FabricBitstream& fabric_bitstream,
-                                 const e_config_protocol_type& sram_orgz_type,
+                                 const ConfigProtocol& config_protocol,
                                  const CircuitLibrary& circuit_lib,
                                  const std::vector<CircuitPortId>& global_ports,
                                  const AtomContext& atom_ctx,
@@ -1494,17 +1691,36 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
   /* Preparation: find all the clock ports */
   std::vector<std::string> clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation);
 
+  /* Preparation: find all the reset/set ports for programming usage */
+  std::vector<CircuitPortId> global_prog_reset_ports = find_global_programming_reset_ports(circuit_lib, global_ports);
+  std::vector<CircuitPortId> global_prog_set_ports = find_global_programming_set_ports(circuit_lib, global_ports);
+
+  /* Identify if we can apply fast configuration */
+  bool apply_fast_configuration = fast_configuration;
+  if ( (global_prog_set_ports.empty() && global_prog_reset_ports.empty())
+     && (true == fast_configuration)) {
+    VTR_LOG_WARN("None of global reset and set ports are defined for programming purpose. Fast configuration is turned off\n");
+    apply_fast_configuration = false;
+  }
+  bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol.type(),
+                                                                         apply_fast_configuration,
+                                                                         global_prog_reset_ports, 
+                                                                         global_prog_set_ports, 
+                                                                         bitstream_manager, fabric_bitstream);
+
   /* Start of testbench */
   print_verilog_top_testbench_ports(fp, module_manager, top_module,
                                     atom_ctx, netlist_annotation, clock_port_names,
-                                    sram_orgz_type, circuit_name);
+                                    config_protocol, circuit_lib,
+                                    circuit_name);
 
   /* Find the clock period */
   float prog_clock_period = (1./simulation_parameters.programming_clock_frequency());
   float op_clock_period = (1./simulation_parameters.operating_clock_frequency());
   /* Estimate the number of configuration clock cycles */
-  size_t num_config_clock_cycles = calculate_num_config_clock_cycles(sram_orgz_type,
-                                                                     fast_configuration,
+  size_t num_config_clock_cycles = calculate_num_config_clock_cycles(config_protocol.type(),
+                                                                     apply_fast_configuration,
+                                                                     bit_value_to_skip,
                                                                      bitstream_manager,
                                                                      fabric_bitstream);
 
@@ -1515,10 +1731,38 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
                                                op_clock_period,
                                                VERILOG_SIM_TIMESCALE);
 
+  /* Identify the stimulus for global reset/set for programming purpose:
+   * - If only reset port is seen we turn on Reset 
+   * - If only set port is seen we turn on Reset 
+   * - If both reset and set port is defined,
+   *   we pick the one which is consistent with the bit value to be skipped
+   */
+  bool active_global_prog_reset = false; 
+  bool active_global_prog_set = false; 
+
+  if (!global_prog_reset_ports.empty()) {
+    active_global_prog_reset = true;
+  }
+
+  if (!global_prog_set_ports.empty()) {
+    active_global_prog_set = true;
+  }
+
+  /* Ensure that at most only one of the two switches is activated */
+  if ( (true == active_global_prog_reset)
+    && (true == active_global_prog_set) ) { 
+    /* If we will skip logic '0', we will activate programming reset */
+    active_global_prog_reset = !bit_value_to_skip;
+    /* If we will skip logic '1', we will activate programming set */
+    active_global_prog_set = bit_value_to_skip;
+  }
+
   /* Generate stimuli for global ports or connect them to existed signals */
   print_verilog_top_testbench_global_ports_stimuli(fp,
                                                    module_manager, top_module,
-                                                   circuit_lib, global_ports);
+                                                   circuit_lib, global_ports,
+                                                   active_global_prog_reset,
+                                                   active_global_prog_set);
 
   /* Instanciate FPGA top-level module */
   print_verilog_testbench_fpga_instance(fp, module_manager, top_module,
@@ -1542,12 +1786,13 @@ void print_verilog_top_testbench(const ModuleManager& module_manager,
 
   /* Print tasks used for loading bitstreams */
   print_verilog_top_testbench_load_bitstream_task(fp,
-                                                  sram_orgz_type,
+                                                  config_protocol.type(),
                                                   module_manager, top_module);
 
   /* load bitstream to FPGA fabric in a configuration phase */
-  print_verilog_top_testbench_bitstream(fp, sram_orgz_type,
-                                        fast_configuration,
+  print_verilog_top_testbench_bitstream(fp, config_protocol.type(),
+                                        apply_fast_configuration,
+                                        bit_value_to_skip,
                                         module_manager, top_module,
                                         bitstream_manager, fabric_bitstream);
 

openfpga/src/fpga_verilog/verilog_top_testbench.h

@@ -10,6 +10,7 @@
 #include "bitstream_manager.h"
 #include "fabric_bitstream.h"
 #include "circuit_library.h"
+#include "config_protocol.h"
 #include "vpr_context.h"
 #include "io_location_map.h"
 #include "vpr_netlist_annotation.h"
@@ -25,7 +26,7 @@ namespace openfpga {
 void print_verilog_top_testbench(const ModuleManager& module_manager,
                                  const BitstreamManager& bitstream_manager,
                                  const FabricBitstream& fabric_bitstream,
-                                 const e_config_protocol_type& sram_orgz_type,
+                                 const ConfigProtocol& config_protocol,
                                  const CircuitLibrary& circuit_lib,
                                  const std::vector<CircuitPortId>& global_ports,
                                  const AtomContext& atom_ctx,

openfpga/test_blif/and.act

@@ -1,3 +0,0 @@
-a 0.5 0.5
-b 0.5 0.5
-c 0.25 0.25

openfpga/test_blif/and.blif

@@ -1,8 +0,0 @@
-.model top
-.inputs a b
-.outputs c
-
-.names a b c
-11 1
-
-.end

openfpga/test_blif/and.v

@@ -1,14 +0,0 @@
-`timescale 1ns / 1ps
-
-module top(
-  a,
-  b,
-  c);
-
-input wire a;
-input wire b;
-output wire c;
-
-assign c = a & b;
-
-endmodule

openfpga/test_blif/and_latch.act

@@ -1,6 +0,0 @@
-a 0.492800 0.201000
-b 0.502000 0.197200
-clk 0.500000 2.000000
-d 0.240200 0.171200
-c 0.240200 0.044100
-n1 0.240200 0.044100

openfpga/test_blif/and_latch.blif

@@ -1,14 +0,0 @@
-# Benchmark "top" written by ABC on Wed Mar 11 10:36:28 2020
-.model top
-.inputs a b clk
-.outputs c d
-
-.latch n1 d  re clk 0
-
-.names a b c
-11 1
-
-.names c n1
-1 1
-
-.end

openfpga/test_blif/and_latch.v

@@ -1,23 +0,0 @@
-`timescale 1ns / 1ps
-
-module top(
-  clk,
-  a,
-  b,
-  c,
-  d);
-
-input wire clk;
-
-input wire a;
-input wire b;
-output wire c;
-output reg d;
-
-assign c = a & b;
-
-always @(posedge clk) begin
-  d <= c;
-end
-
-endmodule

openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml

@@ -1,285 +0,0 @@
-<!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k6_N10_40nm.xml 
-     - General purpose logic block
-       - K = 6, N = 10, I = 40
-       - Single mode
-     - Routing architecture
-       - L = 4, fc_in = 0.15, fc_out = 0.1
-  -->
-<openfpga_architecture>
-  <technology_library>
-    <device_library>
-      <device_model name="logic" type="transistor">
-        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="0.9" pn_ratio="2"/>
-        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-      </device_model>
-      <device_model name="io" type="transistor">
-        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="2.5" pn_ratio="3"/>
-        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-      </device_model>
-    </device_library>
-    <variation_library>
-      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-    </variation_library>
-  </technology_library>
-  <circuit_library>
-    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
-      <design_technology type="cmos" topology="inverter" size="1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
-      <design_technology type="cmos" topology="OR"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
-      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="input" prefix="sel" size="1"/>
-      <port type="input" prefix="selb" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
-        10e-12 5e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
-        10e-12 5e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
-    </circuit_model>
-    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
-    </circuit_model>
-    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="INVTX1"/>
-       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
-    </circuit_model>
-    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
-      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
-      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
-      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="64"/>
-      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-    </circuit_model>
-    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="INVTX1"/>
-       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
-    </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
-    </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="input" prefix="cin" size="1"/>
-      <port type="output" prefix="sumout" size="1"/>
-      <port type="output" prefix="cout" size="1"/>
-    </circuit_model>
-  </circuit_library>
-  <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
-  </configuration_protocol>
-  <connection_block>
-    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
-  </connection_block>
-  <switch_block>
-    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
-  </switch_block>
-  <routing_segment>
-    <segment name="L4" circuit_model_name="chan_segment"/>
-  </routing_segment>
-  <direct_connection>
-    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-  </direct_connection>
-  <pb_type_annotations>
-    <!-- physical pb_type binding in complex block IO -->
-    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
-    <!-- End physical pb_type binding in complex block IO -->
-
-    <!-- physical pb_type binding in complex block CLB -->
-    <!-- physical mode will be the default mode if not specified -->
-    <pb_type name="clb">
-      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
-      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
-    </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
-    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <!-- Binding operating pb_types in mode 'n2_lut5' -->
-    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:4]"/>
-      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'arithmetic' -->
-    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
-      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:3]"/>
-      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
-    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'ble6' -->
-    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
-      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:5]"/>
-      <port name="out" physical_mode_port="lut6_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
-    <!-- End physical pb_type binding in complex block IO -->
-  </pb_type_annotations>
-</openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>

openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml

@@ -1,302 +0,0 @@
-<!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k6_N10_40nm.xml 
-     - General purpose logic block
-       - K = 6, N = 10, I = 40
-       - Single mode
-     - Routing architecture
-       - L = 4, fc_in = 0.15, fc_out = 0.1
-  -->
-<openfpga_architecture>
-  <technology_library>
-    <device_library>
-      <device_model name="logic" type="transistor">
-        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="0.9" pn_ratio="2"/>
-        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-      </device_model>
-      <device_model name="io" type="transistor">
-        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="2.5" pn_ratio="3"/>
-        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-      </device_model>
-    </device_library>
-    <variation_library>
-      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-    </variation_library>
-  </technology_library>
-  <circuit_library>
-    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
-      <design_technology type="cmos" topology="inverter" size="1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
-      <design_technology type="cmos" topology="OR"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
-      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="input" prefix="sel" size="1"/>
-      <port type="input" prefix="selb" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
-        10e-12 5e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
-        10e-12 5e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
-    </circuit_model>
-    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
-    </circuit_model>
-    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="INVTX1"/>
-       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
-    </circuit_model>
-    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
-      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
-      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
-      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="64"/>
-      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-    </circuit_model>
-    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="INVTX1"/>
-       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
-    </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
-    </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="input" prefix="cin" size="1"/>
-      <port type="output" prefix="sumout" size="1"/>
-      <port type="output" prefix="cout" size="1"/>
-    </circuit_model>
-    <circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpsram.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="waddr" size="10"/>
-      <port type="input" prefix="raddr" size="10"/>
-      <port type="input" prefix="d_in" size="32"/>
-      <port type="input" prefix="wen" size="1"/>
-      <port type="input" prefix="ren" size="1"/>
-      <port type="output" prefix="d_out" size="32"/>
-      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
-    </circuit_model>
-  </circuit_library>
-  <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
-  </configuration_protocol>
-  <connection_block>
-    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
-  </connection_block>
-  <switch_block>
-    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
-  </switch_block>
-  <routing_segment>
-    <segment name="L4" circuit_model_name="chan_segment"/>
-  </routing_segment>
-  <direct_connection>
-    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-  </direct_connection>
-  <pb_type_annotations>
-    <!-- physical pb_type binding in complex block IO -->
-    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
-    <!-- End physical pb_type binding in complex block IO -->
-
-    <!-- physical pb_type binding in complex block CLB -->
-    <!-- physical mode will be the default mode if not specified -->
-    <pb_type name="clb">
-      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
-      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
-    </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
-    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <!-- Binding operating pb_types in mode 'n2_lut5' -->
-    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:4]"/>
-      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'arithmetic' -->
-    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
-      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:3]"/>
-      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
-    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'ble6' -->
-    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
-      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:5]"/>
-      <port name="out" physical_mode_port="lut6_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
-    <!-- End physical pb_type binding in complex block clb -->
-
-
-    <!-- physical pb_type binding in complex block memory -->
-    <pb_type name="memory[mem_512x32_dp].mem_512x32_dp" circuit_model_name="dpram_512x32"/>
-    <!-- END physical pb_type binding in complex block memory -->
-  </pb_type_annotations>
-</openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>

openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml

@@ -1,314 +0,0 @@
-<!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k6_N10_40nm.xml 
-     - General purpose logic block
-       - K = 6, N = 10, I = 40
-       - Single mode
-     - Routing architecture
-       - L = 4, fc_in = 0.15, fc_out = 0.1
-  -->
-<openfpga_architecture>
-  <technology_library>
-    <device_library>
-      <device_model name="logic" type="transistor">
-        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="0.9" pn_ratio="2"/>
-        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-      </device_model>
-      <device_model name="io" type="transistor">
-        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="2.5" pn_ratio="3"/>
-        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-      </device_model>
-    </device_library>
-    <variation_library>
-      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-    </variation_library>
-  </technology_library>
-  <circuit_library>
-    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
-      <design_technology type="cmos" topology="inverter" size="1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
-      <design_technology type="cmos" topology="OR"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
-      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="input" prefix="sel" size="1"/>
-      <port type="input" prefix="selb" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
-        10e-12 5e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
-        10e-12 5e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
-    </circuit_model>
-    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
-    </circuit_model>
-    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="INVTX1"/>
-       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
-    </circuit_model>
-    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
-      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
-      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
-      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="64"/>
-      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-    </circuit_model>
-    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="INVTX1"/>
-       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
-    </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
-    </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="input" prefix="cin" size="1"/>
-      <port type="output" prefix="sumout" size="1"/>
-      <port type="output" prefix="cout" size="1"/>
-    </circuit_model>
-    <circuit_model type="hard_logic" name="dpram_512x32" prefix="dpram_512x32" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpsram.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="waddr" size="10"/>
-      <port type="input" prefix="raddr" size="10"/>
-      <port type="input" prefix="d_in" size="32"/>
-      <port type="input" prefix="wen" size="1"/>
-      <port type="input" prefix="ren" size="1"/>
-      <port type="output" prefix="d_out" size="32"/>
-      <port type="clock" prefix="clk" size="1" is_global="true" default_val="0"/>
-    </circuit_model>
-    <circuit_model type="iopad" name="aib" prefix="aib" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/aib.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/aib.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="tx_data" size="80"/>
-      <port type="output" prefix="rx_data" size="80"/>
-      <port type="clock" prefix="tx_clk" size="1" default_val="0"/>
-      <port type="clock" prefix="rx_clk" size="1" default_val="0"/>
-      <port type="inout" prefix="pad" size="80" is_global="true" is_io="true"/>
-    </circuit_model>
-  </circuit_library>
-  <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
-  </configuration_protocol>
-  <connection_block>
-    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
-  </connection_block>
-  <switch_block>
-    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
-  </switch_block>
-  <routing_segment>
-    <segment name="L4" circuit_model_name="chan_segment"/>
-  </routing_segment>
-  <direct_connection>
-    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-  </direct_connection>
-  <pb_type_annotations>
-    <!-- physical pb_type binding in complex block AIB-->
-    <pb_type name="aib[physical].aib_core" circuit_model_name="aib"/>
-    <!-- physical pb_type binding in complex block IO -->
-    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
-    <!-- End physical pb_type binding in complex block IO -->
-
-    <!-- physical pb_type binding in complex block CLB -->
-    <!-- physical mode will be the default mode if not specified -->
-    <pb_type name="clb">
-      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
-      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
-    </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
-    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <!-- Binding operating pb_types in mode 'n2_lut5' -->
-    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:4]"/>
-      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'arithmetic' -->
-    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
-      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:3]"/>
-      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
-    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'ble6' -->
-    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
-      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:5]"/>
-      <port name="out" physical_mode_port="lut6_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
-    <!-- End physical pb_type binding in complex block clb -->
-
-
-    <!-- physical pb_type binding in complex block memory -->
-    <pb_type name="memory[mem_512x32_dp].mem_512x32_dp" circuit_model_name="dpram_512x32"/>
-    <!-- END physical pb_type binding in complex block memory -->
-  </pb_type_annotations>
-</openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>

openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml

@@ -1,288 +0,0 @@
-<!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k6_N10_40nm.xml 
-     - General purpose logic block
-       - K = 6, N = 10, I = 40
-       - Single mode
-     - Routing architecture
-       - L = 4, fc_in = 0.15, fc_out = 0.1
-  -->
-<openfpga_architecture>
-  <technology_library>
-    <device_library>
-      <device_model name="logic" type="transistor">
-        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="0.9" pn_ratio="2"/>
-        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-      </device_model>
-      <device_model name="io" type="transistor">
-        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="2.5" pn_ratio="3"/>
-        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-      </device_model>
-    </device_library>
-    <variation_library>
-      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-    </variation_library>
-  </technology_library>
-  <circuit_library>
-    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
-      <design_technology type="cmos" topology="inverter" size="1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
-      <design_technology type="cmos" topology="OR"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
-      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="input" prefix="sel" size="1"/>
-      <port type="input" prefix="selb" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
-        10e-12 5e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
-        10e-12 5e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
-    </circuit_model>
-    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
-    </circuit_model>
-    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="INVTX1"/>
-       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
-    </circuit_model>
-    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
-      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
-      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
-      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="64"/>
-      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-    </circuit_model>
-    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="INVTX1"/>
-       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
-    </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
-    </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="input" prefix="cin" size="1"/>
-      <port type="output" prefix="sumout" size="1"/>
-      <port type="output" prefix="cout" size="1"/>
-    </circuit_model>
-  </circuit_library>
-  <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
-  </configuration_protocol>
-  <connection_block>
-    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
-  </connection_block>
-  <switch_block>
-    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
-  </switch_block>
-  <routing_segment>
-    <segment name="L4" circuit_model_name="chan_segment"/>
-  </routing_segment>
-  <direct_connection>
-    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-    <direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-  </direct_connection>
-  <pb_type_annotations>
-    <!-- physical pb_type binding in complex block IO -->
-    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
-    <!-- End physical pb_type binding in complex block IO -->
-
-    <!-- physical pb_type binding in complex block CLB -->
-    <!-- physical mode will be the default mode if not specified -->
-    <pb_type name="clb">
-      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
-      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
-    </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
-    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <!-- Binding operating pb_types in mode 'n2_lut5' -->
-    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:4]"/>
-      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'arithmetic' -->
-    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
-      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:3]"/>
-      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
-    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'ble6' -->
-    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
-      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:5]"/>
-      <port name="out" physical_mode_port="lut6_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
-    <!-- Binding operating pb_types in mode 'shift_register' -->
-    <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- End physical pb_type binding in complex block IO -->
-  </pb_type_annotations>
-</openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>

openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml

@@ -1,294 +0,0 @@
-<!-- Architecture annotation for OpenFPGA framework
-     This annotation supports the k6_N10_40nm.xml 
-     - General purpose logic block
-       - K = 6, N = 10, I = 40
-       - Single mode
-     - Routing architecture
-       - L = 4, fc_in = 0.15, fc_out = 0.1
-  -->
-<openfpga_architecture>
-  <technology_library>
-    <device_library>
-      <device_model name="logic" type="transistor">
-        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="0.9" pn_ratio="2"/>
-        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
-      </device_model>
-      <device_model name="io" type="transistor">
-        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
-        <design vdd="2.5" pn_ratio="3"/>
-        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
-      </device_model>
-    </device_library>
-    <variation_library>
-      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
-    </variation_library>
-  </technology_library>
-  <circuit_library>
-    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
-      <design_technology type="cmos" topology="inverter" size="1"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
-      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in" out_port="out">
-        10e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
-      <design_technology type="cmos" topology="OR"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
-      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="input" prefix="sel" size="1"/>
-      <port type="input" prefix="selb" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
-        10e-12 5e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
-        10e-12 5e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
-    </circuit_model>
-    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
-      <design_technology type="cmos"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
-    </circuit_model>
-    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
-      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="1"/>
-    </circuit_model>
-    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> 
-        This is flip-flop with scan-chain feature.
-        When the TESTEN is enabled, the data will be propagated form DI instead of D
-      -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="INVTX1"/>
-       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="DI" size="1"/>
-       <port type="input" prefix="TESTEN" size="1" is_global="true" default_val="0"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
-    </circuit_model>
-    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
-      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
-      <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
-      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
-      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="64"/>
-      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-    </circuit_model>
-    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
-       <design_technology type="cmos"/>
-       <input_buffer exist="true" circuit_model_name="INVTX1"/>
-       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
-    </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
-    </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="input" prefix="cin" size="1"/>
-      <port type="output" prefix="sumout" size="1"/>
-      <port type="output" prefix="cout" size="1"/>
-    </circuit_model>
-  </circuit_library>
-  <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
-  </configuration_protocol>
-  <connection_block>
-    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
-  </connection_block>
-  <switch_block>
-    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
-  </switch_block>
-  <routing_segment>
-    <segment name="L4" circuit_model_name="chan_segment"/>
-  </routing_segment>
-  <direct_connection>
-    <direct name="adder_carry" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-    <direct name="shift_register" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-    <direct name="scan_chain" circuit_model_name="direct_interc" type="column" x_dir="positive" y_dir="positive"/>
-  </direct_connection>
-  <pb_type_annotations>
-    <!-- physical pb_type binding in complex block IO -->
-    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
-    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
-    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
-    <!-- End physical pb_type binding in complex block IO -->
-
-    <!-- physical pb_type binding in complex block CLB -->
-    <!-- physical mode will be the default mode if not specified -->
-    <pb_type name="clb">
-      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
-      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
-    </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
-    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <!-- Binding operating pb_types in mode 'n2_lut5' -->
-    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:4]"/>
-      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'arithmetic' -->
-    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
-      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:3]"/>
-      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
-    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'ble6' -->
-    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
-      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:5]"/>
-      <port name="out" physical_mode_port="lut6_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
-    <!-- Binding operating pb_types in mode 'shift_register' -->
-    <pb_type name="clb.fle[shift_register].shift_reg.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- End physical pb_type binding in complex block IO -->
-  </pb_type_annotations>
-</openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>

openfpga/test_script/and_k6_frac.openfpga

@@ -1,62 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges --verbose
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin #--verbose
-
-write_fabric_hierarchy --file ./fabric_hierarchy.txt
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/and.bitstream
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --hierarchical --file /var/tmp/xtang/openfpga_test_src/SDC_hie
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_k6_frac_adder_chain.openfpga

@@ -1,62 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Write GSB to XML for debugging
-write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin --verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga

@@ -1,62 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Write GSB to XML for debugging
-write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin --verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_k6_frac_tileable.openfpga

@@ -1,59 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin #--verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga

@@ -1,64 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Write GSB to XML for debugging
-write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin --verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
- write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC \
-  --explicit_port_mapping --include_timing --include_signal_init \
-  --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga

@@ -1,62 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Write GSB to XML for debugging
-write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin --verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga

@@ -1,62 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Write GSB to XML for debugging
-write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin --verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga

@@ -1,62 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Write GSB to XML for debugging
-write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin --verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga

@@ -1,62 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Write GSB to XML for debugging
-write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin --verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga

@@ -1,62 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Write GSB to XML for debugging
-write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin --verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga

@@ -1,63 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Write GSB to XML for debugging
-write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin --verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc \
- --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_k6_frac_tileable_spyio.openfpga

@@ -1,59 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin #--verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga

@@ -1,59 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin #--verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga

@@ -1,62 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Write GSB to XML for debugging
-write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin --verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga

@@ -1,59 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin #--verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_latch_k6_frac.openfpga

@@ -1,59 +0,0 @@
-# Run VPR for the 'and_latch' design
-vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/and_latch.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin #--verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack --verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_latch_k6_frac_tileable.openfpga

@@ -1,59 +0,0 @@
-# Run VPR for the 'and_latch' design
-vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and_latch.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin #--verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack --verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga

@@ -1,62 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and_latch.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Write GSB to XML for debugging
-write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin --verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga

@@ -1,62 +0,0 @@
-# Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml ./test_blif/and_latch.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
-
-# Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml
-
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
-
-# Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Write GSB to XML for debugging
-write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
-
-# Check and correct any naming conflicts in the BLIF netlist
-check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
-
-# Apply fix-up to clustering nets based on routing results
-pb_pin_fixup --verbose
-
-# Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
-
-# Build the module graph 
-#  - Enabled compression on routing architecture modules
-#  - Enable pin duplication on grid modules 
-build_fabric --compress_routing --duplicate_grid_pin --verbose
-
-# Repack the netlist to physical pbs
-# This must be done before bitstream generator and testbench generation
-# Strongly recommend it is done after all the fix-up have been applied
-repack #--verbose
-
-# Build the bitstream 
-#  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
-
-# Build fabric-dependent bitstream
-build_fabric_bitstream --verbose
-
-# Write the Verilog netlist for FPGA fabric
-#  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
-
-# Write the Verilog testbench for FPGA fabric
-#  - We suggest the use of same output directory as fabric Verilog netlists
-#  - Must specify the reference benchmark file if you want to output any testbenches
-#  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
-#  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
-#  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
-
-# Write the SDC files for PnR backend
-#  - Turn on every options here 
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
-
-# Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
-
-# Finish and exit OpenFPGA
-exit

openfpga/test_vpr_arch/k6_N10_40nm.xml

@@ -1,299 +0,0 @@
-<!-- 
-  Architecture with no fracturable LUTs
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.  This architecture has no fracturable LUTs nor any heterogeneous blocks.
-
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--->
-<architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
-  -->
-  <models>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="io">
-      <input_ports>
-        <port name="outpad"/>
-      </input_ports>
-      <output_ports>
-        <port name="inpad"/>
-      </output_ports>
-    </model>
-  </models>
-  <tiles>
-    <tile name="io" capacity="8" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <clock name="clock" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad io.clock</loc>
-        <loc side="top">io.outpad io.inpad io.clock</loc>
-        <loc side="right">io.outpad io.inpad io.clock</loc>
-        <loc side="bottom">io.outpad io.inpad io.clock</loc>
-      </pinlocations>
-    </tile>
-    <tile name="clb" area="53894">
-      <equivalent_sites>
-        <site pb_type="clb"/>
-      </equivalent_sites>
-      <input name="I" num_pins="40" equivalent="full"/>
-      <output name="O" num_pins="10" equivalent="instance"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
-  <layout tileable="false">
-    <auto_layout aspect_ratio="1.0">
-      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
-      <perimeter type="io" priority="100"/>
-      <corners type="EMPTY" priority="101"/>
-      <!--Fill with 'clb'-->
-      <fill type="clb" priority="10"/>
-    </auto_layout>
-  </layout>
-  <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
-    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	  -->
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="wilton" fs="3"/>
-    <connection_block input_switch_name="ipin_cblock"/>
-  </device>
-  <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-	       book area formula. This means the mux transistors are about 5x minimum drive strength.
-	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-	       2.5x when looking up in Jeff's tables.
-	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
-  </switchlist>
-  <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
-      <mux name="0"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-  </segmentlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <clock name="clock" num_pins="1"/>
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->
-      <mode name="physical" packable="false">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
-          </direct>
-          <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-      <power method="ignore"/>
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
-    <pb_type name="clb">
-      <input name="I" num_pins="40" equivalent="full"/>
-      <output name="O" num_pins="10" equivalent="instance"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Describe basic logic element.  
-             Each basic logic element has a 6-LUT that can be optionally registered
-        -->
-      <pb_type name="fle" num_pb="10">
-        <input name="in" num_pins="6"/>
-        <output name="out" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <!-- 6-LUT mode definition begin -->
-        <mode name="n1_lut6">
-          <!-- Define 6-LUT mode -->
-          <pb_type name="ble6" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Define LUT -->
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="6" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                261e-12
-                261e-12
-                261e-12
-                261e-12
-                261e-12
-                261e-12
-              </delay_matrix>
-            </pb_type>
-            <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
-              <direct name="direct2" input="lut6.out" output="ff.D">
-                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
-                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="ble6.in"/>
-            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
-            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
-          </interconnect>
-        </mode>
-        <!-- 6-LUT mode definition end -->
-      </pb_type>
-      <interconnect>
-        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
-		     The delays below come from Stratix IV. the delay through a connection block
-		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-		     delay within the crossbar is 95 ps. 
-		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-		     to get the part that should be marked on the crossbar.	 -->
-        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
-          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
-          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
-        </complete>
-        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-        </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-               naive specification).
-          -->
-        <direct name="clbouts1" input="fle[9:0].out" output="clb.O"/>
-      </interconnect>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- Place this general purpose logic block in any unspecified column -->
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-  </complexblocklist>
-</architecture>

openfpga/test_vpr_arch/k6_frac_N10_40nm.xml

@@ -1,441 +0,0 @@
-<!-- 
-  Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with all 5 inputs shared) 
-    with optionally registered outputs
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--->
-<architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
-  -->
-  <models>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="io">
-      <input_ports>
-        <port name="outpad"/>
-      </input_ports>
-      <output_ports>
-        <port name="inpad"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="frac_lut6">
-      <input_ports>
-        <port name="in"/>
-      </input_ports>
-      <output_ports>
-        <port name="lut5_out"/>
-        <port name="lut6_out"/>
-      </output_ports>
-    </model>
-  </models>
-  <tiles>
-    <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
-         If you need to register the I/O, define clocks in the circuit models
-         These clocks can be handled in back-end
-     -->
-    <tile name="io" capacity="8" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad</loc>
-        <loc side="top">io.outpad io.inpad</loc>
-        <loc side="right">io.outpad io.inpad</loc>
-        <loc side="bottom">io.outpad io.inpad</loc>
-      </pinlocations>
-    </tile>
-    <tile name="clb" area="53894">
-      <equivalent_sites>
-        <site pb_type="clb"/>
-      </equivalent_sites>
-      <input name="I" num_pins="40" equivalent="full"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
-  <layout tileable="false">
-    <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="2x2" width="4" height="4">
-      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
-      <perimeter type="io" priority="100"/>
-      <corners type="EMPTY" priority="101"/>
-      <!--Fill with 'clb'-->
-      <fill type="clb" priority="10"/>
-    </fixed_layout>
-    <!-- /auto_layout -->
-  </layout>
-  <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
-    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	  -->
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
-    <connection_block input_switch_name="ipin_cblock"/>
-  </device>
-  <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-	       book area formula. This means the mux transistors are about 5x minimum drive strength.
-	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-	       2.5x when looking up in Jeff's tables.
-	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
-  </switchlist>
-  <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
-      <mux name="0"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-  </segmentlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
-           If you need to register the I/O, define clocks in the circuit models
-           These clocks can be handled in back-end
-       -->
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->
-      <mode name="physical" packable="false">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
-          </direct>
-          <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-      <power method="ignore"/>
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
-    <pb_type name="clb">
-      <input name="I" num_pins="40" equivalent="full"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Describe fracturable logic element.  
-             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
-             The outputs of the fracturable logic element can be optionally registered
-        -->
-      <pb_type name="fle" num_pb="10">
-        <input name="in" num_pins="6"/>
-        <output name="out" num_pins="2"/>
-        <clock name="clk" num_pins="1"/>
-        <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" packable="false">
-          <pb_type name="fabric" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="2"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="frac_logic" num_pb="1">
-              <input name="in" num_pins="6"/>
-              <output name="out" num_pins="2"/>
-              <!-- Define LUT -->
-              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
-                <input name="in" num_pins="6"/>
-                <output name="lut5_out" num_pins="2"/>
-                <output name="lut6_out" num_pins="1"/>
-              </pb_type>
-              <interconnect>
-                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
-                <direct name="direct2" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
-                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
-                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
-              </interconnect>
-            </pb_type>
-            <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
-              <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
-                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
-              </mux>
-              <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
-                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="fabric.in"/>
-            <direct name="direct2" input="fabric.out" output="fle.out"/>
-            <direct name="direct3" input="fle.clk" output="fabric.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Physical mode definition end (physical implementation of the fle) -->
-        <!-- Dual 5-LUT mode definition begin -->
-        <mode name="n2_lut5">
-          <pb_type name="lut5inter" num_pb="1">
-            <input name="in" num_pins="5"/>
-            <output name="out" num_pins="2"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="ble5" num_pb="2">
-              <input name="in" num_pins="5"/>
-              <output name="out" num_pins="1"/>
-              <clock name="clk" num_pins="1"/>
-              <!-- Define the LUT -->
-              <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-                <input name="in" num_pins="5" port_class="lut_in"/>
-                <output name="out" num_pins="1" port_class="lut_out"/>
-                <!-- LUT timing using delay matrix -->
-                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                           we instead take the average of these numbers to get more stable results
-                      82e-12
-                      173e-12
-                      261e-12
-                      263e-12
-                      398e-12
-                      -->
-                <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                  235e-12
-                  235e-12
-                  235e-12
-                  235e-12
-                  235e-12
-                </delay_matrix>
-              </pb_type>
-              <!-- Define the flip-flop -->
-              <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-                <input name="D" num_pins="1" port_class="D"/>
-                <output name="Q" num_pins="1" port_class="Q"/>
-                <clock name="clk" num_pins="1" port_class="clock"/>
-                <T_setup value="66e-12" port="ff.D" clock="clk"/>
-                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-              </pb_type>
-              <interconnect>
-                <direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
-                <direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
-                  <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
-                  <pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/>
-                </direct>
-                <direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/>
-                <mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]">
-                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                  <delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/>
-                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/>
-                </mux>
-              </interconnect>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
-              <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
-              <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
-              <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
-            <direct name="direct2" input="lut5inter.out" output="fle.out"/>
-            <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Dual 5-LUT mode definition end -->
-        <!-- 6-LUT mode definition begin -->
-        <mode name="n1_lut6">
-          <!-- Define 6-LUT mode -->
-          <pb_type name="ble6" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Define LUT -->
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="6" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                261e-12
-                261e-12
-                261e-12
-                261e-12
-                261e-12
-                261e-12
-              </delay_matrix>
-            </pb_type>
-            <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
-              <direct name="direct2" input="lut6.out" output="ff.D">
-                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
-                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="ble6.in"/>
-            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
-            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
-          </interconnect>
-        </mode>
-        <!-- 6-LUT mode definition end -->
-      </pb_type>
-      <interconnect>
-        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
-		     The delays below come from Stratix IV. the delay through a connection block
-		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-		     delay within the crossbar is 95 ps. 
-		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-		     to get the part that should be marked on the crossbar.	 -->
-        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
-          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
-          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
-        </complete>
-        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-        </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-               naive specification).
-          -->
-        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
-        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
-      </interconnect>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- Place this general purpose logic block in any unspecified column -->
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-  </complexblocklist>
-</architecture>

openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml

@@ -1,644 +0,0 @@
-<!-- 
-  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
-    with optionally registered outputs
-    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
-    Carry chain links to vertically adjacent logic blocks
-  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
-    Height = 6, found on every (8n+2)th column
-  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
-    Height = 4, found on every (8n+6)th column
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  The electrical design of the architecture described here is NOT from an 
-  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
-  architecture file by using an existing commercial FPGA to approximate the area, 
-  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
-  model of wiring and circuit design for low-level routing components, where available.
-  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
-  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
-  modified and you will still get reasonable delay results for the new architecture.
-  The following describes, in detail, how we obtained the various electrical values for this 
-  architecture.
-
-  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
-  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
-  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
-  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
-  match the overall target (a 40 nm FPGA).
-
-  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
-  memories, and multipliers from test circuits on a Stratix IV GX device 
-  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
-  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
-  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
-  take the R and C data from the ITRS roadmap.  
-
-  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
-  crossbar is close enough to the crossbar modelled here.  
-  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
-  36:1 multiplexers.  We match these parameters in this architecture.
-
-  For LUTs, we include LUT 
-  delays measured from Stratix IV which is dependant on the input used (ie. some 
-  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
-  not consider differences in LUT input delays.
-
-  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
-  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
-  all pins except clock virtual) then measuring the delays in chip-planner, 
-  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
-  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
-  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
-  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
-  overhead that we don't have, I'll approximate the delay of a simpler chain at 
-  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
-  can be justified).
-
-  Logic block area numbers obtained by scaling overall tile area of a 65nm 
-  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
-  routing area at a channel width of 300. We use a channel width of 300 because it can route 
-  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
-  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
-  choosing a width that provides high routability. The architecture can be routed at different channel
-  widths, but we estimate the tile size and hence the physical length of routing wires assuming
-  a channel width of 300.
-
-  Sanity checks employed:
-    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
-        common electrical design.
-
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--->
-<architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
-  -->
-  <models>
-    <model name="adder">
-      <input_ports>
-        <port name="a" combinational_sink_ports="sumout cout"/>
-        <port name="b" combinational_sink_ports="sumout cout"/>
-        <port name="cin" combinational_sink_ports="sumout cout"/>
-      </input_ports>
-      <output_ports>
-        <port name="cout"/>
-        <port name="sumout"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="io">
-      <input_ports>
-        <port name="outpad"/>
-      </input_ports>
-      <output_ports>
-        <port name="inpad"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="frac_lut6">
-      <input_ports>
-        <port name="in"/>
-      </input_ports>
-      <output_ports>
-        <port name="lut4_out"/>
-        <port name="lut5_out"/>
-        <port name="lut6_out"/>
-      </output_ports>
-    </model>
-  </models>
-  <tiles>
-    <tile name="io" capacity="8" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad</loc>
-        <loc side="top">io.outpad io.inpad</loc>
-        <loc side="right">io.outpad io.inpad</loc>
-        <loc side="bottom">io.outpad io.inpad</loc>
-      </pinlocations>
-    </tile>
-    <tile name="clb" area="53894">
-      <equivalent_sites>
-        <site pb_type="clb"/>
-      </equivalent_sites>
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
-      </fc>
-      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
-      <!--pinlocations pattern="spread"/-->
-      <pinlocations pattern="custom">
-        <loc side="left">clb.clk</loc>
-        <loc side="top">clb.cin</loc>
-        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
-        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
-      </pinlocations>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
-  <layout tileable="false">
-    <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="6" height="6">
-      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
-      <perimeter type="io" priority="100"/>
-      <corners type="EMPTY" priority="101"/>
-      <!--Fill with 'clb'-->
-      <fill type="clb" priority="10"/>
-    </fixed_layout>
-    <!-- /auto_layout -->
-  </layout>
-  <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
-    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	    -->
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="wilton" fs="3"/>
-    <connection_block input_switch_name="ipin_cblock"/>
-  </device>
-  <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-           book area formula. This means the mux transistors are about 5x minimum drive strength.
-           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-           2.5x when looking up in Jeff's tables.
-           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
-  </switchlist>
-  <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
-      <mux name="0"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-  </segmentlist>
-  <directlist>
-    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
-  </directlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-
-      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
-           If you need to register the I/O, define clocks in the circuit models
-           These clocks can be handled in back-end
-       -->
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->
-      <mode name="physical" packable="false">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
-          </direct>
-          <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-      <power method="ignore"/>
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
-    <pb_type name="clb">
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Describe fracturable logic element.  
-             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
-             The outputs of the fracturable logic element can be optionally registered
-        -->
-      <pb_type name="fle" num_pb="10">
-        <input name="in" num_pins="6"/>
-        <input name="cin" num_pins="1"/>
-        <output name="out" num_pins="2"/>
-        <output name="cout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" packable="false">
-          <pb_type name="fabric" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="2"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="frac_logic" num_pb="1">
-              <input name="in" num_pins="6"/>
-              <output name="lut4_out" num_pins="4"/>
-              <output name="out" num_pins="2"/>
-              <!-- Define LUT -->
-              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
-                <input name="in" num_pins="6"/>
-                <output name="lut4_out" num_pins="4"/>
-                <output name="lut5_out" num_pins="2"/>
-                <output name="lut6_out" num_pins="1"/>
-              </pb_type>
-              <interconnect>
-                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
-                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
-                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
-                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
-                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
-              </interconnect>
-            </pb_type>
-            <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>         
-            <!-- Define adders -->
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
-                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
-              </mux>
-              <mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
-                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
-              </mux>
-              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
-                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
-              </mux>
-              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
-                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="fabric.in"/>
-            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
-            <direct name="direct3" input="fabric.out" output="fle.out"/>
-            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
-            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Physical mode definition end (physical implementation of the fle) -->
-        <!-- BEGIN fle mode of dual lut5 -->
-        <mode name="n2_lut5">
-          <pb_type name="ble5" num_pb="2">
-            <input name="in" num_pins="5"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Regular LUT mode -->
-            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="5" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                  we instead take the average of these numbers to get more stable results
-                82e-12
-                173e-12
-                261e-12
-                263e-12
-                398e-12
-                -->
-              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-              </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble5.in" output="lut5.in"/>
-              <direct name="direct2" input="lut5.out" output="ff.D">
-                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
-                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
-            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
-            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
-            <direct name="direct4" input="ble5.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- END fle mode of dual lut5 -->
-        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
-        <mode name="arithmetic">
-          <pb_type name="arithmetic" num_pb="2">
-            <input name="in" num_pins="4"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="1"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Special dual-LUT mode that drives adder only -->
-            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
-              <input name="in" num_pins="4" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  -->
-              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                  195e-12
-                  195e-12
-                  195e-12
-                  195e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
-              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
-              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
-              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
-                </direct>
-              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
-                </direct>
-              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
-                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
-              </direct>
-              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
-                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
-              </direct>
-              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
-                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
-              </direct>
-              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
-                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
-            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
-            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
-              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
-            </direct>
-            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
-              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
-            </direct>
-            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
-              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
-            </direct>
-            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
-            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- n2_lut5 -->
-        <mode name="n1_lut6">
-          <pb_type name="ble6" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="6" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
-              <direct name="direct2" input="lut6.out" output="ff.D">
-                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
-            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
-            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
-          </interconnect>
-        </mode>
-        <!-- n1_lut6 -->
-      </pb_type>
-      <interconnect>
-        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
-           The delays below come from Stratix IV. the delay through a connection block
-           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-           delay within the crossbar is 95 ps. 
-           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-           to get the part that should be marked on the crossbar.	 -->
-        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
-          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
-          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
-        </complete>
-
-        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-        </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-                 naive specification).
-          -->
-        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
-        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
-        <!-- Carry chain links -->
-        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
-          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
-        </direct>
-        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
-          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
-        </direct>
-        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
-          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
-        </direct>
-      </interconnect>
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-  </complexblocklist>
-</architecture>

openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml

@@ -1,739 +0,0 @@
-<!-- 
-  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
-    with optionally registered outputs
-    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
-    Carry chain links to vertically adjacent logic blocks
-  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
-    Height = 6, found on every (8n+2)th column
-  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
-    Height = 4, found on every (8n+6)th column
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  The electrical design of the architecture described here is NOT from an 
-  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
-  architecture file by using an existing commercial FPGA to approximate the area, 
-  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
-  model of wiring and circuit design for low-level routing components, where available.
-  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
-  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
-  modified and you will still get reasonable delay results for the new architecture.
-  The following describes, in detail, how we obtained the various electrical values for this 
-  architecture.
-
-  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
-  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
-  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
-  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
-  match the overall target (a 40 nm FPGA).
-
-  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
-  memories, and multipliers from test circuits on a Stratix IV GX device 
-  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
-  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
-  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
-  take the R and C data from the ITRS roadmap.  
-
-  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
-  crossbar is close enough to the crossbar modelled here.  
-  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
-  36:1 multiplexers.  We match these parameters in this architecture.
-
-  For LUTs, we include LUT 
-  delays measured from Stratix IV which is dependant on the input used (ie. some 
-  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
-  not consider differences in LUT input delays.
-
-  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
-  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
-  all pins except clock virtual) then measuring the delays in chip-planner, 
-  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
-  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
-  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
-  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
-  overhead that we don't have, I'll approximate the delay of a simpler chain at 
-  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
-  can be justified).
-
-  Logic block area numbers obtained by scaling overall tile area of a 65nm 
-  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
-  routing area at a channel width of 300. We use a channel width of 300 because it can route 
-  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
-  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
-  choosing a width that provides high routability. The architecture can be routed at different channel
-  widths, but we estimate the tile size and hence the physical length of routing wires assuming
-  a channel width of 300.
-
-  Sanity checks employed:
-    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
-        common electrical design.
-
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--->
-<architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
-  -->
-  <models>
-    <model name="adder">
-      <input_ports>
-        <port name="a" combinational_sink_ports="sumout cout"/>
-        <port name="b" combinational_sink_ports="sumout cout"/>
-        <port name="cin" combinational_sink_ports="sumout cout"/>
-      </input_ports>
-      <output_ports>
-        <port name="cout"/>
-        <port name="sumout"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="io">
-      <input_ports>
-        <port name="outpad"/>
-      </input_ports>
-      <output_ports>
-        <port name="inpad"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="frac_lut6">
-      <input_ports>
-        <port name="in"/>
-      </input_ports>
-      <output_ports>
-        <port name="lut4_out"/>
-        <port name="lut5_out"/>
-        <port name="lut6_out"/>
-      </output_ports>
-    </model>
-    <model name="dual_port_ram">
-      <input_ports>
-        <!-- write address lines -->
-        <port name="waddr" clock="clk"/>
-        <!-- read address lines -->
-        <port name="raddr" clock="clk"/>
-        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
-        <port name="d_in" clock="clk"/>
-        <!-- write enable -->
-        <port name="wen" clock="clk"/>
-        <!-- read enable -->
-        <port name="ren" clock="clk"/>
-        <!-- memories are often clocked -->
-        <port name="clk" is_clock="1"/>
-      </input_ports>
-      <output_ports>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-        <port name="d_out" clock="clk"/>
-      </output_ports>
-    </model>
-  </models>
-  <tiles>
-    <tile name="io" capacity="8" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad</loc>
-        <loc side="top">io.outpad io.inpad</loc>
-        <loc side="right">io.outpad io.inpad</loc>
-        <loc side="bottom">io.outpad io.inpad</loc>
-      </pinlocations>
-    </tile>
-    <tile name="clb" area="53894">
-      <equivalent_sites>
-        <site pb_type="clb"/>
-      </equivalent_sites>
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
-      </fc>
-      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
-      <!--pinlocations pattern="spread"/-->
-      <pinlocations pattern="custom">
-        <loc side="left">clb.clk</loc>
-        <loc side="top">clb.cin</loc>
-        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
-        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
-      </pinlocations>
-    </tile>
-    <tile name="memory" height="2" area="548000">
-      <equivalent_sites>
-        <site pb_type="memory"/>
-      </equivalent_sites>
-      <input name="waddr" num_pins="10"/>
-      <input name="raddr" num_pins="10"/>
-      <input name="d_in" num_pins="32"/>
-      <input name="wen" num_pins="1"/>
-      <input name="ren" num_pins="1"/>
-      <output name="d_out" num_pins="32"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
-  <layout tileable="false">
-    <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="5" height="4">
-      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
-      <perimeter type="io" priority="100"/>
-      <corners type="EMPTY" priority="101"/>
-      <!--Fill with 'clb'-->
-      <fill type="clb" priority="10"/>
-      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
-      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
-      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-    </fixed_layout>
-    <!-- /auto_layout -->
-  </layout>
-  <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
-    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	    -->
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="wilton" fs="3"/>
-    <connection_block input_switch_name="ipin_cblock"/>
-  </device>
-  <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-           book area formula. This means the mux transistors are about 5x minimum drive strength.
-           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-           2.5x when looking up in Jeff's tables.
-           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
-  </switchlist>
-  <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
-      <mux name="0"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-  </segmentlist>
-  <directlist>
-    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
-  </directlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-
-      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
-           If you need to register the I/O, define clocks in the circuit models
-           These clocks can be handled in back-end
-       -->
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->
-      <mode name="physical" packable="false">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
-          </direct>
-          <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-      <power method="ignore"/>
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
-    <pb_type name="clb">
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Describe fracturable logic element.  
-             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
-             The outputs of the fracturable logic element can be optionally registered
-        -->
-      <pb_type name="fle" num_pb="10">
-        <input name="in" num_pins="6"/>
-        <input name="cin" num_pins="1"/>
-        <output name="out" num_pins="2"/>
-        <output name="cout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" packable="false">
-          <pb_type name="fabric" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="2"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="frac_logic" num_pb="1">
-              <input name="in" num_pins="6"/>
-              <output name="lut4_out" num_pins="4"/>
-              <output name="out" num_pins="2"/>
-              <!-- Define LUT -->
-              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
-                <input name="in" num_pins="6"/>
-                <output name="lut4_out" num_pins="4"/>
-                <output name="lut5_out" num_pins="2"/>
-                <output name="lut6_out" num_pins="1"/>
-              </pb_type>
-              <interconnect>
-                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
-                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
-                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
-                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
-                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
-              </interconnect>
-            </pb_type>
-            <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>         
-            <!-- Define adders -->
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
-                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
-              </mux>
-              <mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
-                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
-              </mux>
-              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
-                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
-              </mux>
-              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
-                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="fabric.in"/>
-            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
-            <direct name="direct3" input="fabric.out" output="fle.out"/>
-            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
-            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Physical mode definition end (physical implementation of the fle) -->
-        <!-- BEGIN fle mode of dual lut5 -->
-        <mode name="n2_lut5">
-          <pb_type name="ble5" num_pb="2">
-            <input name="in" num_pins="5"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Regular LUT mode -->
-            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="5" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                  we instead take the average of these numbers to get more stable results
-                82e-12
-                173e-12
-                261e-12
-                263e-12
-                398e-12
-                -->
-              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-              </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble5.in" output="lut5.in"/>
-              <direct name="direct2" input="lut5.out" output="ff.D">
-                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
-                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
-            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
-            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
-            <direct name="direct4" input="ble5.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- END fle mode of dual lut5 -->
-        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
-        <mode name="arithmetic">
-          <pb_type name="arithmetic" num_pb="2">
-            <input name="in" num_pins="4"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="1"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Special dual-LUT mode that drives adder only -->
-            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
-              <input name="in" num_pins="4" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  -->
-              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                  195e-12
-                  195e-12
-                  195e-12
-                  195e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
-              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
-              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
-              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
-                </direct>
-              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
-                </direct>
-              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
-                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
-              </direct>
-              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
-                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
-              </direct>
-              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
-                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
-              </direct>
-              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
-                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
-            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
-            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
-              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
-            </direct>
-            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
-              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
-            </direct>
-            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
-              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
-            </direct>
-            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
-            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- n2_lut5 -->
-        <mode name="n1_lut6">
-          <pb_type name="ble6" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="6" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
-              <direct name="direct2" input="lut6.out" output="ff.D">
-                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
-            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
-            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
-          </interconnect>
-        </mode>
-        <!-- n1_lut6 -->
-      </pb_type>
-      <interconnect>
-        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
-           The delays below come from Stratix IV. the delay through a connection block
-           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-           delay within the crossbar is 95 ps. 
-           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-           to get the part that should be marked on the crossbar.	 -->
-        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
-          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
-          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
-        </complete>
-
-        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-        </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-                 naive specification).
-          -->
-        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
-        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
-        <!-- Carry chain links -->
-        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
-          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
-        </direct>
-        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
-          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
-        </direct>
-        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
-          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
-        </direct>
-      </interconnect>
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-    <!-- Define single-mode dual-port memory begin -->
-    <pb_type name="memory">
-      <input name="waddr" num_pins="10"/>
-      <input name="raddr" num_pins="10"/>
-      <input name="d_in" num_pins="32"/>
-      <input name="wen" num_pins="1"/>
-      <input name="ren" num_pins="1"/>
-      <output name="d_out" num_pins="32"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Specify the 512x32=16Kbit memory block
-           Note: the delay numbers are extracted from VPR flagship XML without modification
-                 Should align to the process technology we using to create the 16K dual-port RAM
-        -->
-      <mode name="mem_512x32_dp">
-        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="waddr" num_pins="10" port_class="address"/>
-          <input name="raddr" num_pins="10" port_class="address"/>
-          <input name="d_in" num_pins="32" port_class="data_in"/>
-          <input name="wen" num_pins="1" port_class="write_en"/>
-          <input name="ren" num_pins="1" port_class="write_en"/>
-          <output name="d_out" num_pins="32" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="17.9e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
-            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
-          </direct>
-          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
-            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
-          </direct>
-          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
-            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
-          </direct>
-          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
-            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
-          </direct>
-          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
-            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
-          </direct>
-          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
-            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-    </pb_type>
-    <!-- Define single-mode dual-port memory end -->
-  </complexblocklist>
-</architecture>

openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml

@@ -1,441 +0,0 @@
-<!-- 
-  Flagship Heterogeneous Architecture (No Carry Chains) for VTR 7.0.
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with all 5 inputs shared) 
-    with optionally registered outputs
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  Based on flagship k6_frac_N10_mem32K_40nm.xml architecture.
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--->
-<architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
-  -->
-  <models>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="io">
-      <input_ports>
-        <port name="outpad"/>
-      </input_ports>
-      <output_ports>
-        <port name="inpad"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="frac_lut6">
-      <input_ports>
-        <port name="in"/>
-      </input_ports>
-      <output_ports>
-        <port name="lut5_out"/>
-        <port name="lut6_out"/>
-      </output_ports>
-    </model>
-  </models>
-  <tiles>
-    <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
-         If you need to register the I/O, define clocks in the circuit models
-         These clocks can be handled in back-end
-     -->
-    <tile name="io" capacity="8" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad</loc>
-        <loc side="top">io.outpad io.inpad</loc>
-        <loc side="right">io.outpad io.inpad</loc>
-        <loc side="bottom">io.outpad io.inpad</loc>
-      </pinlocations>
-    </tile>
-    <tile name="clb" area="53894">
-      <equivalent_sites>
-        <site pb_type="clb"/>
-      </equivalent_sites>
-      <input name="I" num_pins="40" equivalent="full"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
-  <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="2x2" width="4" height="4">
-      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
-      <perimeter type="io" priority="100"/>
-      <corners type="EMPTY" priority="101"/>
-      <!--Fill with 'clb'-->
-      <fill type="clb" priority="10"/>
-    </fixed_layout>
-    <!-- /auto_layout -->
-  </layout>
-  <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
-    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	  -->
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="wilton" fs="3" sub_type="subset" sub_fs="3"/>
-    <connection_block input_switch_name="ipin_cblock"/>
-  </device>
-  <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-	       book area formula. This means the mux transistors are about 5x minimum drive strength.
-	       We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-	       mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-	       the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-	       by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-	       buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-	       I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-	       (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-	       The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-	       2.5x when looking up in Jeff's tables.
-	       Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-	       This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
-  </switchlist>
-  <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-			     With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-			     reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
-      <mux name="0"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-  </segmentlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
-           If you need to register the I/O, define clocks in the circuit models
-           These clocks can be handled in back-end
-       -->
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->
-      <mode name="physical" packable="false">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
-          </direct>
-          <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-      <power method="ignore"/>
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
-    <pb_type name="clb">
-      <input name="I" num_pins="40" equivalent="full"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Describe fracturable logic element.  
-             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
-             The outputs of the fracturable logic element can be optionally registered
-        -->
-      <pb_type name="fle" num_pb="10">
-        <input name="in" num_pins="6"/>
-        <output name="out" num_pins="2"/>
-        <clock name="clk" num_pins="1"/>
-        <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" packable="false">
-          <pb_type name="fabric" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="2"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="frac_logic" num_pb="1">
-              <input name="in" num_pins="6"/>
-              <output name="out" num_pins="2"/>
-              <!-- Define LUT -->
-              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
-                <input name="in" num_pins="6"/>
-                <output name="lut5_out" num_pins="2"/>
-                <output name="lut6_out" num_pins="1"/>
-              </pb_type>
-              <interconnect>
-                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
-                <direct name="direct2" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
-                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
-                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
-              </interconnect>
-            </pb_type>
-            <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
-              <complete name="direct3" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
-                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
-              </mux>
-              <mux name="mux2" input="ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
-                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="fabric.in"/>
-            <direct name="direct2" input="fabric.out" output="fle.out"/>
-            <direct name="direct3" input="fle.clk" output="fabric.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Physical mode definition end (physical implementation of the fle) -->
-        <!-- Dual 5-LUT mode definition begin -->
-        <mode name="n2_lut5">
-          <pb_type name="lut5inter" num_pb="1">
-            <input name="in" num_pins="5"/>
-            <output name="out" num_pins="2"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="ble5" num_pb="2">
-              <input name="in" num_pins="5"/>
-              <output name="out" num_pins="1"/>
-              <clock name="clk" num_pins="1"/>
-              <!-- Define the LUT -->
-              <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-                <input name="in" num_pins="5" port_class="lut_in"/>
-                <output name="out" num_pins="1" port_class="lut_out"/>
-                <!-- LUT timing using delay matrix -->
-                <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                           we instead take the average of these numbers to get more stable results
-                      82e-12
-                      173e-12
-                      261e-12
-                      263e-12
-                      398e-12
-                      -->
-                <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                  235e-12
-                  235e-12
-                  235e-12
-                  235e-12
-                  235e-12
-                </delay_matrix>
-              </pb_type>
-              <!-- Define the flip-flop -->
-              <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-                <input name="D" num_pins="1" port_class="D"/>
-                <output name="Q" num_pins="1" port_class="Q"/>
-                <clock name="clk" num_pins="1" port_class="clock"/>
-                <T_setup value="66e-12" port="ff.D" clock="clk"/>
-                <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-              </pb_type>
-              <interconnect>
-                <direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
-                <direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
-                  <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
-                  <pack_pattern name="ble5" in_port="lut5[0:0].out" out_port="ff[0:0].D"/>
-                </direct>
-                <direct name="direct3" input="ble5.clk" output="ff[0:0].clk"/>
-                <mux name="mux1" input="ff[0:0].Q lut5.out[0:0]" output="ble5.out[0:0]">
-                  <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                  <delay_constant max="25e-12" in_port="lut5.out[0:0]" out_port="ble5.out[0:0]"/>
-                  <delay_constant max="45e-12" in_port="ff[0:0].Q" out_port="ble5.out[0:0]"/>
-                </mux>
-              </interconnect>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="lut5inter.in" output="ble5[0:0].in"/>
-              <direct name="direct2" input="lut5inter.in" output="ble5[1:1].in"/>
-              <direct name="direct3" input="ble5[1:0].out" output="lut5inter.out"/>
-              <complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
-            <direct name="direct2" input="lut5inter.out" output="fle.out"/>
-            <direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Dual 5-LUT mode definition end -->
-        <!-- 6-LUT mode definition begin -->
-        <mode name="n1_lut6">
-          <!-- Define 6-LUT mode -->
-          <pb_type name="ble6" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Define LUT -->
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="6" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                261e-12
-                261e-12
-                261e-12
-                261e-12
-                261e-12
-                261e-12
-              </delay_matrix>
-            </pb_type>
-            <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
-              <direct name="direct2" input="lut6.out" output="ff.D">
-                <!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
-                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="ble6.in"/>
-            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
-            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
-          </interconnect>
-        </mode>
-        <!-- 6-LUT mode definition end -->
-      </pb_type>
-      <interconnect>
-        <!-- We use a full crossbar to get logical equivalence at inputs of CLB 
-		     The delays below come from Stratix IV. the delay through a connection block
-		     input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-		     delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-		     delay within the crossbar is 95 ps. 
-		     The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-		     Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-		     25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-		     to get the part that should be marked on the crossbar.	 -->
-        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
-          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
-          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
-        </complete>
-        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-        </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-               By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-               then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-               naive specification).
-          -->
-        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
-        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
-      </interconnect>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- Place this general purpose logic block in any unspecified column -->
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-  </complexblocklist>
-</architecture>

openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml

@@ -1,644 +0,0 @@
-<!-- 
-  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
-    with optionally registered outputs
-    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
-    Carry chain links to vertically adjacent logic blocks
-  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
-    Height = 6, found on every (8n+2)th column
-  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
-    Height = 4, found on every (8n+6)th column
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  The electrical design of the architecture described here is NOT from an 
-  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
-  architecture file by using an existing commercial FPGA to approximate the area, 
-  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
-  model of wiring and circuit design for low-level routing components, where available.
-  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
-  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
-  modified and you will still get reasonable delay results for the new architecture.
-  The following describes, in detail, how we obtained the various electrical values for this 
-  architecture.
-
-  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
-  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
-  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
-  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
-  match the overall target (a 40 nm FPGA).
-
-  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
-  memories, and multipliers from test circuits on a Stratix IV GX device 
-  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
-  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
-  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
-  take the R and C data from the ITRS roadmap.  
-
-  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
-  crossbar is close enough to the crossbar modelled here.  
-  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
-  36:1 multiplexers.  We match these parameters in this architecture.
-
-  For LUTs, we include LUT 
-  delays measured from Stratix IV which is dependant on the input used (ie. some 
-  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
-  not consider differences in LUT input delays.
-
-  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
-  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
-  all pins except clock virtual) then measuring the delays in chip-planner, 
-  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
-  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
-  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
-  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
-  overhead that we don't have, I'll approximate the delay of a simpler chain at 
-  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
-  can be justified).
-
-  Logic block area numbers obtained by scaling overall tile area of a 65nm 
-  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
-  routing area at a channel width of 300. We use a channel width of 300 because it can route 
-  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
-  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
-  choosing a width that provides high routability. The architecture can be routed at different channel
-  widths, but we estimate the tile size and hence the physical length of routing wires assuming
-  a channel width of 300.
-
-  Sanity checks employed:
-    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
-        common electrical design.
-
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--->
-<architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
-  -->
-  <models>
-    <model name="adder">
-      <input_ports>
-        <port name="a" combinational_sink_ports="sumout cout"/>
-        <port name="b" combinational_sink_ports="sumout cout"/>
-        <port name="cin" combinational_sink_ports="sumout cout"/>
-      </input_ports>
-      <output_ports>
-        <port name="cout"/>
-        <port name="sumout"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="io">
-      <input_ports>
-        <port name="outpad"/>
-      </input_ports>
-      <output_ports>
-        <port name="inpad"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="frac_lut6">
-      <input_ports>
-        <port name="in"/>
-      </input_ports>
-      <output_ports>
-        <port name="lut4_out"/>
-        <port name="lut5_out"/>
-        <port name="lut6_out"/>
-      </output_ports>
-    </model>
-  </models>
-  <tiles>
-    <tile name="io" capacity="8" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad</loc>
-        <loc side="top">io.outpad io.inpad</loc>
-        <loc side="right">io.outpad io.inpad</loc>
-        <loc side="bottom">io.outpad io.inpad</loc>
-      </pinlocations>
-    </tile>
-    <tile name="clb" area="53894">
-      <equivalent_sites>
-        <site pb_type="clb"/>
-      </equivalent_sites>
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
-      </fc>
-      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
-      <!--pinlocations pattern="spread"/-->
-      <pinlocations pattern="custom">
-        <loc side="left">clb.clk</loc>
-        <loc side="top">clb.cin</loc>
-        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
-        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
-      </pinlocations>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
-  <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="6" height="6">
-      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
-      <perimeter type="io" priority="100"/>
-      <corners type="EMPTY" priority="101"/>
-      <!--Fill with 'clb'-->
-      <fill type="clb" priority="10"/>
-    </fixed_layout>
-    <!-- /auto_layout -->
-  </layout>
-  <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
-    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	    -->
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="wilton" fs="3"/>
-    <connection_block input_switch_name="ipin_cblock"/>
-  </device>
-  <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-           book area formula. This means the mux transistors are about 5x minimum drive strength.
-           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-           2.5x when looking up in Jeff's tables.
-           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
-  </switchlist>
-  <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
-      <mux name="0"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-  </segmentlist>
-  <directlist>
-    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
-  </directlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-
-      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
-           If you need to register the I/O, define clocks in the circuit models
-           These clocks can be handled in back-end
-       -->
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->
-      <mode name="physical" packable="false">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
-          </direct>
-          <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-      <power method="ignore"/>
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
-    <pb_type name="clb">
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Describe fracturable logic element.  
-             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
-             The outputs of the fracturable logic element can be optionally registered
-        -->
-      <pb_type name="fle" num_pb="10">
-        <input name="in" num_pins="6"/>
-        <input name="cin" num_pins="1"/>
-        <output name="out" num_pins="2"/>
-        <output name="cout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" packable="false">
-          <pb_type name="fabric" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="2"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="frac_logic" num_pb="1">
-              <input name="in" num_pins="6"/>
-              <output name="lut4_out" num_pins="4"/>
-              <output name="out" num_pins="2"/>
-              <!-- Define LUT -->
-              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
-                <input name="in" num_pins="6"/>
-                <output name="lut4_out" num_pins="4"/>
-                <output name="lut5_out" num_pins="2"/>
-                <output name="lut6_out" num_pins="1"/>
-              </pb_type>
-              <interconnect>
-                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
-                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
-                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
-                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
-                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
-              </interconnect>
-            </pb_type>
-            <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>         
-            <!-- Define adders -->
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
-                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
-              </mux>
-              <mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
-                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
-              </mux>
-              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
-                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
-              </mux>
-              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
-                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="fabric.in"/>
-            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
-            <direct name="direct3" input="fabric.out" output="fle.out"/>
-            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
-            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Physical mode definition end (physical implementation of the fle) -->
-        <!-- BEGIN fle mode of dual lut5 -->
-        <mode name="n2_lut5">
-          <pb_type name="ble5" num_pb="2">
-            <input name="in" num_pins="5"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Regular LUT mode -->
-            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="5" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                  we instead take the average of these numbers to get more stable results
-                82e-12
-                173e-12
-                261e-12
-                263e-12
-                398e-12
-                -->
-              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-              </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble5.in" output="lut5.in"/>
-              <direct name="direct2" input="lut5.out" output="ff.D">
-                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
-                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
-            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
-            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
-            <direct name="direct4" input="ble5.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- END fle mode of dual lut5 -->
-        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
-        <mode name="arithmetic">
-          <pb_type name="arithmetic" num_pb="2">
-            <input name="in" num_pins="4"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="1"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Special dual-LUT mode that drives adder only -->
-            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
-              <input name="in" num_pins="4" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  -->
-              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                  195e-12
-                  195e-12
-                  195e-12
-                  195e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
-              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
-              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
-              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
-                </direct>
-              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
-                </direct>
-              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
-                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
-              </direct>
-              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
-                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
-              </direct>
-              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
-                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
-              </direct>
-              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
-                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
-            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
-            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
-              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
-            </direct>
-            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
-              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
-            </direct>
-            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
-              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
-            </direct>
-            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
-            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- n2_lut5 -->
-        <mode name="n1_lut6">
-          <pb_type name="ble6" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="6" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
-              <direct name="direct2" input="lut6.out" output="ff.D">
-                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
-            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
-            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
-          </interconnect>
-        </mode>
-        <!-- n1_lut6 -->
-      </pb_type>
-      <interconnect>
-        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
-           The delays below come from Stratix IV. the delay through a connection block
-           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-           delay within the crossbar is 95 ps. 
-           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-           to get the part that should be marked on the crossbar.	 -->
-        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
-          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
-          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
-        </complete>
-
-        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-        </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-                 naive specification).
-          -->
-        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
-        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
-        <!-- Carry chain links -->
-        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
-          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
-        </direct>
-        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
-          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
-        </direct>
-        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
-          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
-        </direct>
-      </interconnect>
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-  </complexblocklist>
-</architecture>

openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml

@@ -1,739 +0,0 @@
-<!-- 
-  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
-    with optionally registered outputs
-    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
-    Carry chain links to vertically adjacent logic blocks
-  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
-    Height = 6, found on every (8n+2)th column
-  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
-    Height = 4, found on every (8n+6)th column
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  The electrical design of the architecture described here is NOT from an 
-  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
-  architecture file by using an existing commercial FPGA to approximate the area, 
-  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
-  model of wiring and circuit design for low-level routing components, where available.
-  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
-  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
-  modified and you will still get reasonable delay results for the new architecture.
-  The following describes, in detail, how we obtained the various electrical values for this 
-  architecture.
-
-  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
-  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
-  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
-  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
-  match the overall target (a 40 nm FPGA).
-
-  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
-  memories, and multipliers from test circuits on a Stratix IV GX device 
-  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
-  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
-  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
-  take the R and C data from the ITRS roadmap.  
-
-  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
-  crossbar is close enough to the crossbar modelled here.  
-  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
-  36:1 multiplexers.  We match these parameters in this architecture.
-
-  For LUTs, we include LUT 
-  delays measured from Stratix IV which is dependant on the input used (ie. some 
-  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
-  not consider differences in LUT input delays.
-
-  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
-  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
-  all pins except clock virtual) then measuring the delays in chip-planner, 
-  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
-  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
-  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
-  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
-  overhead that we don't have, I'll approximate the delay of a simpler chain at 
-  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
-  can be justified).
-
-  Logic block area numbers obtained by scaling overall tile area of a 65nm 
-  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
-  routing area at a channel width of 300. We use a channel width of 300 because it can route 
-  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
-  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
-  choosing a width that provides high routability. The architecture can be routed at different channel
-  widths, but we estimate the tile size and hence the physical length of routing wires assuming
-  a channel width of 300.
-
-  Sanity checks employed:
-    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
-        common electrical design.
-
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--->
-<architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
-  -->
-  <models>
-    <model name="adder">
-      <input_ports>
-        <port name="a" combinational_sink_ports="sumout cout"/>
-        <port name="b" combinational_sink_ports="sumout cout"/>
-        <port name="cin" combinational_sink_ports="sumout cout"/>
-      </input_ports>
-      <output_ports>
-        <port name="cout"/>
-        <port name="sumout"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="io">
-      <input_ports>
-        <port name="outpad"/>
-      </input_ports>
-      <output_ports>
-        <port name="inpad"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="frac_lut6">
-      <input_ports>
-        <port name="in"/>
-      </input_ports>
-      <output_ports>
-        <port name="lut4_out"/>
-        <port name="lut5_out"/>
-        <port name="lut6_out"/>
-      </output_ports>
-    </model>
-    <model name="dual_port_ram">
-      <input_ports>
-        <!-- write address lines -->
-        <port name="waddr" clock="clk"/>
-        <!-- read address lines -->
-        <port name="raddr" clock="clk"/>
-        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
-        <port name="d_in" clock="clk"/>
-        <!-- write enable -->
-        <port name="wen" clock="clk"/>
-        <!-- read enable -->
-        <port name="ren" clock="clk"/>
-        <!-- memories are often clocked -->
-        <port name="clk" is_clock="1"/>
-      </input_ports>
-      <output_ports>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-        <port name="d_out" clock="clk"/>
-      </output_ports>
-    </model>
-  </models>
-  <tiles>
-    <tile name="io" capacity="8" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad</loc>
-        <loc side="top">io.outpad io.inpad</loc>
-        <loc side="right">io.outpad io.inpad</loc>
-        <loc side="bottom">io.outpad io.inpad</loc>
-      </pinlocations>
-    </tile>
-    <tile name="clb" area="53894">
-      <equivalent_sites>
-        <site pb_type="clb"/>
-      </equivalent_sites>
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
-      </fc>
-      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
-      <!--pinlocations pattern="spread"/-->
-      <pinlocations pattern="custom">
-        <loc side="left">clb.clk</loc>
-        <loc side="top">clb.cin</loc>
-        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
-        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
-      </pinlocations>
-    </tile>
-    <tile name="memory" height="2" area="548000">
-      <equivalent_sites>
-        <site pb_type="memory"/>
-      </equivalent_sites>
-      <input name="waddr" num_pins="10"/>
-      <input name="raddr" num_pins="10"/>
-      <input name="d_in" num_pins="32"/>
-      <input name="wen" num_pins="1"/>
-      <input name="ren" num_pins="1"/>
-      <output name="d_out" num_pins="32"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
-  <layout tileable="true" through_channel="false">
-    <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="5" height="4">
-      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
-      <perimeter type="io" priority="100"/>
-      <corners type="EMPTY" priority="101"/>
-      <!--Fill with 'clb'-->
-      <fill type="clb" priority="10"/>
-      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
-      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
-      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-    </fixed_layout>
-    <!-- /auto_layout -->
-  </layout>
-  <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
-    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	    -->
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="wilton" fs="3"/>
-    <connection_block input_switch_name="ipin_cblock"/>
-  </device>
-  <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-           book area formula. This means the mux transistors are about 5x minimum drive strength.
-           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-           2.5x when looking up in Jeff's tables.
-           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
-  </switchlist>
-  <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
-      <mux name="0"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-  </segmentlist>
-  <directlist>
-    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
-  </directlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-
-      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
-           If you need to register the I/O, define clocks in the circuit models
-           These clocks can be handled in back-end
-       -->
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->
-      <mode name="physical" packable="false">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
-          </direct>
-          <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-      <power method="ignore"/>
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
-    <pb_type name="clb">
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Describe fracturable logic element.  
-             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
-             The outputs of the fracturable logic element can be optionally registered
-        -->
-      <pb_type name="fle" num_pb="10">
-        <input name="in" num_pins="6"/>
-        <input name="cin" num_pins="1"/>
-        <output name="out" num_pins="2"/>
-        <output name="cout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" packable="false">
-          <pb_type name="fabric" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="2"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="frac_logic" num_pb="1">
-              <input name="in" num_pins="6"/>
-              <output name="lut4_out" num_pins="4"/>
-              <output name="out" num_pins="2"/>
-              <!-- Define LUT -->
-              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
-                <input name="in" num_pins="6"/>
-                <output name="lut4_out" num_pins="4"/>
-                <output name="lut5_out" num_pins="2"/>
-                <output name="lut6_out" num_pins="1"/>
-              </pb_type>
-              <interconnect>
-                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
-                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
-                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
-                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
-                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
-              </interconnect>
-            </pb_type>
-            <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>         
-            <!-- Define adders -->
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
-                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
-              </mux>
-              <mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
-                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
-              </mux>
-              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
-                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
-              </mux>
-              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
-                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="fabric.in"/>
-            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
-            <direct name="direct3" input="fabric.out" output="fle.out"/>
-            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
-            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Physical mode definition end (physical implementation of the fle) -->
-        <!-- BEGIN fle mode of dual lut5 -->
-        <mode name="n2_lut5">
-          <pb_type name="ble5" num_pb="2">
-            <input name="in" num_pins="5"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Regular LUT mode -->
-            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="5" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                  we instead take the average of these numbers to get more stable results
-                82e-12
-                173e-12
-                261e-12
-                263e-12
-                398e-12
-                -->
-              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-              </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble5.in" output="lut5.in"/>
-              <direct name="direct2" input="lut5.out" output="ff.D">
-                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
-                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
-            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
-            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
-            <direct name="direct4" input="ble5.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- END fle mode of dual lut5 -->
-        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
-        <mode name="arithmetic">
-          <pb_type name="arithmetic" num_pb="2">
-            <input name="in" num_pins="4"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="1"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Special dual-LUT mode that drives adder only -->
-            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
-              <input name="in" num_pins="4" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  -->
-              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                  195e-12
-                  195e-12
-                  195e-12
-                  195e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
-              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
-              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
-              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
-                </direct>
-              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
-                </direct>
-              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
-                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
-              </direct>
-              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
-                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
-              </direct>
-              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
-                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
-              </direct>
-              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
-                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
-            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
-            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
-              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
-            </direct>
-            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
-              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
-            </direct>
-            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
-              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
-            </direct>
-            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
-            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- n2_lut5 -->
-        <mode name="n1_lut6">
-          <pb_type name="ble6" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="6" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
-              <direct name="direct2" input="lut6.out" output="ff.D">
-                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
-            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
-            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
-          </interconnect>
-        </mode>
-        <!-- n1_lut6 -->
-      </pb_type>
-      <interconnect>
-        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
-           The delays below come from Stratix IV. the delay through a connection block
-           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-           delay within the crossbar is 95 ps. 
-           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-           to get the part that should be marked on the crossbar.	 -->
-        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
-          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
-          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
-        </complete>
-
-        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-        </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-                 naive specification).
-          -->
-        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
-        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
-        <!-- Carry chain links -->
-        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
-          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
-        </direct>
-        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
-          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
-        </direct>
-        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
-          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
-        </direct>
-      </interconnect>
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-    <!-- Define single-mode dual-port memory begin -->
-    <pb_type name="memory">
-      <input name="waddr" num_pins="10"/>
-      <input name="raddr" num_pins="10"/>
-      <input name="d_in" num_pins="32"/>
-      <input name="wen" num_pins="1"/>
-      <input name="ren" num_pins="1"/>
-      <output name="d_out" num_pins="32"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Specify the 512x32=16Kbit memory block
-           Note: the delay numbers are extracted from VPR flagship XML without modification
-                 Should align to the process technology we using to create the 16K dual-port RAM
-        -->
-      <mode name="mem_512x32_dp">
-        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="waddr" num_pins="10" port_class="address"/>
-          <input name="raddr" num_pins="10" port_class="address"/>
-          <input name="d_in" num_pins="32" port_class="data_in"/>
-          <input name="wen" num_pins="1" port_class="write_en"/>
-          <input name="ren" num_pins="1" port_class="write_en"/>
-          <output name="d_out" num_pins="32" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="17.9e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
-            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
-          </direct>
-          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
-            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
-          </direct>
-          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
-            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
-          </direct>
-          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
-            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
-          </direct>
-          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
-            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
-          </direct>
-          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
-            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-    </pb_type>
-    <!-- Define single-mode dual-port memory end -->
-  </complexblocklist>
-</architecture>

openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml

@@ -1,805 +0,0 @@
-<!-- 
-  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
-    with optionally registered outputs
-    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
-    Carry chain links to vertically adjacent logic blocks
-  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
-    Height = 6, found on every (8n+2)th column
-  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
-    Height = 4, found on every (8n+6)th column
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  The electrical design of the architecture described here is NOT from an 
-  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
-  architecture file by using an existing commercial FPGA to approximate the area, 
-  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
-  model of wiring and circuit design for low-level routing components, where available.
-  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
-  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
-  modified and you will still get reasonable delay results for the new architecture.
-  The following describes, in detail, how we obtained the various electrical values for this 
-  architecture.
-
-  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
-  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
-  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
-  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
-  match the overall target (a 40 nm FPGA).
-
-  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
-  memories, and multipliers from test circuits on a Stratix IV GX device 
-  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
-  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
-  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
-  take the R and C data from the ITRS roadmap.  
-
-  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
-  crossbar is close enough to the crossbar modelled here.  
-  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
-  36:1 multiplexers.  We match these parameters in this architecture.
-
-  For LUTs, we include LUT 
-  delays measured from Stratix IV which is dependant on the input used (ie. some 
-  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
-  not consider differences in LUT input delays.
-
-  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
-  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
-  all pins except clock virtual) then measuring the delays in chip-planner, 
-  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
-  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
-  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
-  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
-  overhead that we don't have, I'll approximate the delay of a simpler chain at 
-  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
-  can be justified).
-
-  Logic block area numbers obtained by scaling overall tile area of a 65nm 
-  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
-  routing area at a channel width of 300. We use a channel width of 300 because it can route 
-  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
-  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
-  choosing a width that provides high routability. The architecture can be routed at different channel
-  widths, but we estimate the tile size and hence the physical length of routing wires assuming
-  a channel width of 300.
-
-  Sanity checks employed:
-    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
-        common electrical design.
-
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--->
-<architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
-  -->
-  <models>
-    <model name="adder">
-      <input_ports>
-        <port name="a" combinational_sink_ports="sumout cout"/>
-        <port name="b" combinational_sink_ports="sumout cout"/>
-        <port name="cin" combinational_sink_ports="sumout cout"/>
-      </input_ports>
-      <output_ports>
-        <port name="cout"/>
-        <port name="sumout"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="io">
-      <input_ports>
-        <port name="outpad"/>
-      </input_ports>
-      <output_ports>
-        <port name="inpad"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="frac_lut6">
-      <input_ports>
-        <port name="in"/>
-      </input_ports>
-      <output_ports>
-        <port name="lut4_out"/>
-        <port name="lut5_out"/>
-        <port name="lut6_out"/>
-      </output_ports>
-    </model>
-    <model name="dual_port_ram">
-      <input_ports>
-        <!-- write address lines -->
-        <port name="waddr" clock="clk"/>
-        <!-- read address lines -->
-        <port name="raddr" clock="clk"/>
-        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
-        <port name="d_in" clock="clk"/>
-        <!-- write enable -->
-        <port name="wen" clock="clk"/>
-        <!-- read enable -->
-        <port name="ren" clock="clk"/>
-        <!-- memories are often clocked -->
-        <port name="clk" is_clock="1"/>
-      </input_ports>
-      <output_ports>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-        <port name="d_out" clock="clk"/>
-      </output_ports>
-    </model>
-    <!-- AIB interface model -->
-    <model name="aib">
-      <input_ports>
-        <port name="tx_clk" is_clock="1"/>
-        <port name="rx_clk" is_clock="1"/>
-        <port name="tx_data" clock="tx_clk"/>
-      </input_ports>
-      <output_ports>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-        <port name="rx_data" clock="rx_clk"/>
-      </output_ports>
-    </model>
-  </models>
-  <tiles>
-    <tile name="io" capacity="8" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad</loc>
-        <loc side="top">io.outpad io.inpad</loc>
-        <loc side="right">io.outpad io.inpad</loc>
-        <loc side="bottom">io.outpad io.inpad</loc>
-      </pinlocations>
-    </tile>
-    <!-- A mini AIB interface to be located at the right side of the FPGA
-         All the port will be accessible to the left side of the tile
-         TODO: add full control signals
-         TODO: add analog bus ports to the right side which should be GPIOs
-      -->
-    <tile name="aib" width="1" height="4" area="0">
-      <equivalent_sites>
-        <site pb_type="aib"/>
-      </equivalent_sites>
-      <clock name="tx_clk" num_pins="1"/>
-      <input name="tx_data" num_pins="80"/>
-      <clock name="rx_clk" num_pins="1"/>
-      <output name="rx_data" num_pins="80"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">aib.tx_clk aib.tx_data aib.rx_clk aib.rx_data</loc>
-      </pinlocations>
-    </tile>
-    <tile name="clb" area="53894">
-      <equivalent_sites>
-        <site pb_type="clb"/>
-      </equivalent_sites>
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
-      </fc>
-      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
-      <!--pinlocations pattern="spread"/-->
-      <pinlocations pattern="custom">
-        <loc side="left">clb.clk</loc>
-        <loc side="top">clb.cin</loc>
-        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
-        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
-      </pinlocations>
-    </tile>
-    <tile name="memory" height="2" area="548000">
-      <equivalent_sites>
-        <site pb_type="memory"/>
-      </equivalent_sites>
-      <input name="waddr" num_pins="10"/>
-      <input name="raddr" num_pins="10"/>
-      <input name="d_in" num_pins="32"/>
-      <input name="wen" num_pins="1"/>
-      <input name="ren" num_pins="1"/>
-      <output name="d_out" num_pins="32"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
-  <layout tileable="true" through_channel="false">
-    <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="7" height="6">
-      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
-      <perimeter type="io" priority="10"/>
-      <corners type="EMPTY" priority="101"/>
-      <!--Fill with 'clb'-->
-      <fill type="clb" priority="1"/>
-      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
-      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
-      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-      <!-- Single instance of an AIB interface -->
-      <single type="aib" x="6" y="1" priority="20"/>
-    </fixed_layout>
-    <!-- /auto_layout -->
-  </layout>
-  <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
-    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	    -->
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="wilton" fs="3"/>
-    <connection_block input_switch_name="ipin_cblock"/>
-  </device>
-  <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-           book area formula. This means the mux transistors are about 5x minimum drive strength.
-           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-           2.5x when looking up in Jeff's tables.
-           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
-  </switchlist>
-  <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
-      <mux name="0"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-  </segmentlist>
-  <directlist>
-    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
-  </directlist>
-  <complexblocklist>
-    <!-- Define AIB begin -->
-    <pb_type name="aib">
-      <clock name="tx_clk" num_pins="1"/>
-      <input name="tx_data" num_pins="80"/>
-      <clock name="rx_clk" num_pins="1"/>
-      <output name="rx_data" num_pins="80"/>
-      <mode name="physical">
-        <pb_type name="aib_core" blif_model=".subckt aib" num_pb="1">
-          <clock name="tx_clk" num_pins="1"/>
-          <input name="tx_data" num_pins="80"/>
-          <clock name="rx_clk" num_pins="1"/>
-          <output name="rx_data" num_pins="80"/>
-          <T_setup value="509e-12" port="aib_core.tx_data" clock="tx_clk"/>
-          <T_clock_to_Q max="1.234e-9" port="aib_core.tx_data" clock="tx_clk"/>
-          <T_setup value="509e-12" port="aib_core.rx_data" clock="rx_clk"/>
-          <T_clock_to_Q max="1.234e-9" port="aib_core.rx_data" clock="rx_clk"/>
-        </pb_type>
-        <interconnect>
-          <direct name="tx_clk" input="aib.tx_clk" output="aib_core.tx_clk">
-            <delay_constant max="1.394e-11" in_port="aib.tx_clk" out_port="aib_core.tx_clk"/>
-          </direct>
-          <direct name="rx_clk" input="aib.rx_clk" output="aib_core.rx_clk">
-            <delay_constant max="1.394e-11" in_port="aib.rx_clk" out_port="aib_core.rx_clk"/>
-          </direct>
-          <direct name="tx_data" input="aib.tx_data" output="aib_core.tx_data">
-            <delay_constant max="1.394e-11" in_port="aib.tx_data" out_port="aib_core.tx_data"/>
-          </direct>
-          <direct name="rx_data" input="aib_core.rx_data" output="aib.rx_data">
-            <delay_constant max="4.243e-11" in_port="aib_core.rx_data" out_port="aib.rx_data"/>
-          </direct>
-        </interconnect>
-      </mode>
-
-    </pb_type>
-    <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-
-      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
-           If you need to register the I/O, define clocks in the circuit models
-           These clocks can be handled in back-end
-       -->
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->
-      <mode name="physical" packable="false">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
-          </direct>
-          <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-      <power method="ignore"/>
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
-    <pb_type name="clb">
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Describe fracturable logic element.  
-             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
-             The outputs of the fracturable logic element can be optionally registered
-        -->
-      <pb_type name="fle" num_pb="10">
-        <input name="in" num_pins="6"/>
-        <input name="cin" num_pins="1"/>
-        <output name="out" num_pins="2"/>
-        <output name="cout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" packable="false">
-          <pb_type name="fabric" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="2"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="frac_logic" num_pb="1">
-              <input name="in" num_pins="6"/>
-              <output name="lut4_out" num_pins="4"/>
-              <output name="out" num_pins="2"/>
-              <!-- Define LUT -->
-              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
-                <input name="in" num_pins="6"/>
-                <output name="lut4_out" num_pins="4"/>
-                <output name="lut5_out" num_pins="2"/>
-                <output name="lut6_out" num_pins="1"/>
-              </pb_type>
-              <interconnect>
-                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
-                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
-                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
-                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
-                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
-              </interconnect>
-            </pb_type>
-            <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>         
-            <!-- Define adders -->
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
-                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
-              </mux>
-              <mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
-                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
-              </mux>
-              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
-                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
-              </mux>
-              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
-                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="fabric.in"/>
-            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
-            <direct name="direct3" input="fabric.out" output="fle.out"/>
-            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
-            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Physical mode definition end (physical implementation of the fle) -->
-        <!-- BEGIN fle mode of dual lut5 -->
-        <mode name="n2_lut5">
-          <pb_type name="ble5" num_pb="2">
-            <input name="in" num_pins="5"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Regular LUT mode -->
-            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="5" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                  we instead take the average of these numbers to get more stable results
-                82e-12
-                173e-12
-                261e-12
-                263e-12
-                398e-12
-                -->
-              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-              </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble5.in" output="lut5.in"/>
-              <direct name="direct2" input="lut5.out" output="ff.D">
-                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
-                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
-            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
-            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
-            <direct name="direct4" input="ble5.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- END fle mode of dual lut5 -->
-        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
-        <mode name="arithmetic">
-          <pb_type name="arithmetic" num_pb="2">
-            <input name="in" num_pins="4"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="1"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Special dual-LUT mode that drives adder only -->
-            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
-              <input name="in" num_pins="4" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  -->
-              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                  195e-12
-                  195e-12
-                  195e-12
-                  195e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
-              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
-              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
-              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
-                </direct>
-              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
-                </direct>
-              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
-                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
-              </direct>
-              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
-                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
-              </direct>
-              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
-                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
-              </direct>
-              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
-                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
-            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
-            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
-              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
-            </direct>
-            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
-              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
-            </direct>
-            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
-              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
-            </direct>
-            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
-            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- n2_lut5 -->
-        <mode name="n1_lut6">
-          <pb_type name="ble6" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="6" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
-              <direct name="direct2" input="lut6.out" output="ff.D">
-                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
-            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
-            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
-          </interconnect>
-        </mode>
-        <!-- n1_lut6 -->
-      </pb_type>
-      <interconnect>
-        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
-           The delays below come from Stratix IV. the delay through a connection block
-           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-           delay within the crossbar is 95 ps. 
-           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-           to get the part that should be marked on the crossbar.	 -->
-        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
-          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
-          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
-        </complete>
-
-        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-        </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-                 naive specification).
-          -->
-        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
-        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
-        <!-- Carry chain links -->
-        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
-          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
-        </direct>
-        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
-          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
-        </direct>
-        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
-          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
-        </direct>
-      </interconnect>
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-    <!-- Define single-mode dual-port memory begin -->
-    <pb_type name="memory">
-      <input name="waddr" num_pins="10"/>
-      <input name="raddr" num_pins="10"/>
-      <input name="d_in" num_pins="32"/>
-      <input name="wen" num_pins="1"/>
-      <input name="ren" num_pins="1"/>
-      <output name="d_out" num_pins="32"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Specify the 512x32=16Kbit memory block
-           Note: the delay numbers are extracted from VPR flagship XML without modification
-                 Should align to the process technology we using to create the 16K dual-port RAM
-        -->
-      <mode name="mem_512x32_dp">
-        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="waddr" num_pins="10" port_class="address"/>
-          <input name="raddr" num_pins="10" port_class="address"/>
-          <input name="d_in" num_pins="32" port_class="data_in"/>
-          <input name="wen" num_pins="1" port_class="write_en"/>
-          <input name="ren" num_pins="1" port_class="write_en"/>
-          <output name="d_out" num_pins="32" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="17.9e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
-            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
-          </direct>
-          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
-            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
-          </direct>
-          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
-            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
-          </direct>
-          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
-            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
-          </direct>
-          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
-            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
-          </direct>
-          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
-            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-    </pb_type>
-    <!-- Define single-mode dual-port memory end -->
-  </complexblocklist>
-</architecture>

openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml

@@ -1,773 +0,0 @@
-<!-- 
-  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
-    with optionally registered outputs
-    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
-    Carry chain links to vertically adjacent logic blocks
-  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
-    Height = 6, found on every (8n+2)th column
-  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
-    Height = 4, found on every (8n+6)th column
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  The electrical design of the architecture described here is NOT from an 
-  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
-  architecture file by using an existing commercial FPGA to approximate the area, 
-  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
-  model of wiring and circuit design for low-level routing components, where available.
-  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
-  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
-  modified and you will still get reasonable delay results for the new architecture.
-  The following describes, in detail, how we obtained the various electrical values for this 
-  architecture.
-
-  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
-  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
-  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
-  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
-  match the overall target (a 40 nm FPGA).
-
-  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
-  memories, and multipliers from test circuits on a Stratix IV GX device 
-  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
-  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
-  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
-  take the R and C data from the ITRS roadmap.  
-
-  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
-  crossbar is close enough to the crossbar modelled here.  
-  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
-  36:1 multiplexers.  We match these parameters in this architecture.
-
-  For LUTs, we include LUT 
-  delays measured from Stratix IV which is dependant on the input used (ie. some 
-  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
-  not consider differences in LUT input delays.
-
-  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
-  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
-  all pins except clock virtual) then measuring the delays in chip-planner, 
-  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
-  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
-  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
-  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
-  overhead that we don't have, I'll approximate the delay of a simpler chain at 
-  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
-  can be justified).
-
-  Logic block area numbers obtained by scaling overall tile area of a 65nm 
-  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
-  routing area at a channel width of 300. We use a channel width of 300 because it can route 
-  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
-  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
-  choosing a width that provides high routability. The architecture can be routed at different channel
-  widths, but we estimate the tile size and hence the physical length of routing wires assuming
-  a channel width of 300.
-
-  Sanity checks employed:
-    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
-        common electrical design.
-
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--->
-<architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
-  -->
-  <models>
-    <model name="adder">
-      <input_ports>
-        <port name="a" combinational_sink_ports="sumout cout"/>
-        <port name="b" combinational_sink_ports="sumout cout"/>
-        <port name="cin" combinational_sink_ports="sumout cout"/>
-      </input_ports>
-      <output_ports>
-        <port name="cout"/>
-        <port name="sumout"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="io">
-      <input_ports>
-        <port name="outpad"/>
-      </input_ports>
-      <output_ports>
-        <port name="inpad"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="frac_lut6">
-      <input_ports>
-        <port name="in"/>
-      </input_ports>
-      <output_ports>
-        <port name="lut4_out"/>
-        <port name="lut5_out"/>
-        <port name="lut6_out"/>
-      </output_ports>
-    </model>
-    <model name="dual_port_ram">
-      <input_ports>
-        <!-- write address lines -->
-        <port name="waddr" clock="clk"/>
-        <!-- read address lines -->
-        <port name="raddr" clock="clk"/>
-        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
-        <port name="d_in" clock="clk"/>
-        <!-- write enable -->
-        <port name="wen" clock="clk"/>
-        <!-- read enable -->
-        <port name="ren" clock="clk"/>
-        <!-- memories are often clocked -->
-        <port name="clk" is_clock="1"/>
-      </input_ports>
-      <output_ports>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-        <port name="d_out" clock="clk"/>
-      </output_ports>
-    </model>
-  </models>
-  <tiles>
-    <tile name="io_top" capacity="3" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="bottom">io_top.outpad io_top.inpad</loc>
-      </pinlocations>
-    </tile>
-    <tile name="io_right" capacity="2" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">io_right.outpad io_right.inpad</loc>
-      </pinlocations>
-    </tile>
-    <tile name="io_bottom" capacity="1" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="top">io_bottom.outpad io_bottom.inpad</loc>
-      </pinlocations>
-    </tile>
-    <tile name="io_left" capacity="4" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="right">io_left.outpad io_left.inpad</loc>
-      </pinlocations>
-    </tile>
-
-    <tile name="clb" area="53894">
-      <equivalent_sites>
-        <site pb_type="clb"/>
-      </equivalent_sites>
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
-      </fc>
-      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
-      <!--pinlocations pattern="spread"/-->
-      <pinlocations pattern="custom">
-        <loc side="left">clb.clk</loc>
-        <loc side="top">clb.cin</loc>
-        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
-        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
-      </pinlocations>
-    </tile>
-    <tile name="memory" height="2" area="548000">
-      <equivalent_sites>
-        <site pb_type="memory"/>
-      </equivalent_sites>
-      <input name="waddr" num_pins="10"/>
-      <input name="raddr" num_pins="10"/>
-      <input name="d_in" num_pins="32"/>
-      <input name="wen" num_pins="1"/>
-      <input name="ren" num_pins="1"/>
-      <output name="d_out" num_pins="32"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
-  <layout tileable="true" through_channel="false">
-    <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="5" height="4">
-      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
-      <row type="io_top" starty="H-1" priority="100"/>
-      <row type="io_bottom" starty="0" priority="100"/>
-      <col type="io_left" startx="0" priority="100"/>
-      <col type="io_right" startx="W-1" priority="100"/>
-      <corners type="EMPTY" priority="101"/>
-      <!--Fill with 'clb'-->
-      <fill type="clb" priority="10"/>
-      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
-      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
-      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-    </fixed_layout>
-    <!-- /auto_layout -->
-  </layout>
-  <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
-    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	    -->
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="wilton" fs="3"/>
-    <connection_block input_switch_name="ipin_cblock"/>
-  </device>
-  <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-           book area formula. This means the mux transistors are about 5x minimum drive strength.
-           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-           2.5x when looking up in Jeff's tables.
-           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
-  </switchlist>
-  <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
-      <mux name="0"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-  </segmentlist>
-  <directlist>
-    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
-  </directlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-
-      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
-           If you need to register the I/O, define clocks in the circuit models
-           These clocks can be handled in back-end
-       -->
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->
-      <mode name="physical" packable="false">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
-          </direct>
-          <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-      <power method="ignore"/>
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
-    <pb_type name="clb">
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Describe fracturable logic element.  
-             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
-             The outputs of the fracturable logic element can be optionally registered
-        -->
-      <pb_type name="fle" num_pb="10">
-        <input name="in" num_pins="6"/>
-        <input name="cin" num_pins="1"/>
-        <output name="out" num_pins="2"/>
-        <output name="cout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" packable="false">
-          <pb_type name="fabric" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="2"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="frac_logic" num_pb="1">
-              <input name="in" num_pins="6"/>
-              <output name="lut4_out" num_pins="4"/>
-              <output name="out" num_pins="2"/>
-              <!-- Define LUT -->
-              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
-                <input name="in" num_pins="6"/>
-                <output name="lut4_out" num_pins="4"/>
-                <output name="lut5_out" num_pins="2"/>
-                <output name="lut6_out" num_pins="1"/>
-              </pb_type>
-              <interconnect>
-                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
-                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
-                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
-                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
-                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
-              </interconnect>
-            </pb_type>
-            <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>         
-            <!-- Define adders -->
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
-                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
-              </mux>
-              <mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
-                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
-              </mux>
-              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
-                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
-              </mux>
-              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
-                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="fabric.in"/>
-            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
-            <direct name="direct3" input="fabric.out" output="fle.out"/>
-            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
-            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Physical mode definition end (physical implementation of the fle) -->
-        <!-- BEGIN fle mode of dual lut5 -->
-        <mode name="n2_lut5">
-          <pb_type name="ble5" num_pb="2">
-            <input name="in" num_pins="5"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Regular LUT mode -->
-            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="5" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                  we instead take the average of these numbers to get more stable results
-                82e-12
-                173e-12
-                261e-12
-                263e-12
-                398e-12
-                -->
-              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-              </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble5.in" output="lut5.in"/>
-              <direct name="direct2" input="lut5.out" output="ff.D">
-                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
-                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
-            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
-            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
-            <direct name="direct4" input="ble5.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- END fle mode of dual lut5 -->
-        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
-        <mode name="arithmetic">
-          <pb_type name="arithmetic" num_pb="2">
-            <input name="in" num_pins="4"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="1"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Special dual-LUT mode that drives adder only -->
-            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
-              <input name="in" num_pins="4" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  -->
-              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                  195e-12
-                  195e-12
-                  195e-12
-                  195e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
-              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
-              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
-              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
-                </direct>
-              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
-                </direct>
-              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
-                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
-              </direct>
-              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
-                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
-              </direct>
-              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
-                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
-              </direct>
-              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
-                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
-            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
-            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
-              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
-            </direct>
-            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
-              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
-            </direct>
-            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
-              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
-            </direct>
-            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
-            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- n2_lut5 -->
-        <mode name="n1_lut6">
-          <pb_type name="ble6" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="6" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
-              <direct name="direct2" input="lut6.out" output="ff.D">
-                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
-            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
-            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
-          </interconnect>
-        </mode>
-        <!-- n1_lut6 -->
-      </pb_type>
-      <interconnect>
-        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
-           The delays below come from Stratix IV. the delay through a connection block
-           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-           delay within the crossbar is 95 ps. 
-           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-           to get the part that should be marked on the crossbar.	 -->
-        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
-          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
-          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
-        </complete>
-
-        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-        </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-                 naive specification).
-          -->
-        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
-        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
-        <!-- Carry chain links -->
-        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
-          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
-        </direct>
-        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
-          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
-        </direct>
-        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
-          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
-        </direct>
-      </interconnect>
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-    <!-- Define single-mode dual-port memory begin -->
-    <pb_type name="memory">
-      <input name="waddr" num_pins="10"/>
-      <input name="raddr" num_pins="10"/>
-      <input name="d_in" num_pins="32"/>
-      <input name="wen" num_pins="1"/>
-      <input name="ren" num_pins="1"/>
-      <output name="d_out" num_pins="32"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Specify the 512x32=16Kbit memory block
-           Note: the delay numbers are extracted from VPR flagship XML without modification
-                 Should align to the process technology we using to create the 16K dual-port RAM
-        -->
-      <mode name="mem_512x32_dp">
-        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="waddr" num_pins="10" port_class="address"/>
-          <input name="raddr" num_pins="10" port_class="address"/>
-          <input name="d_in" num_pins="32" port_class="data_in"/>
-          <input name="wen" num_pins="1" port_class="write_en"/>
-          <input name="ren" num_pins="1" port_class="write_en"/>
-          <output name="d_out" num_pins="32" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="17.9e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
-            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
-          </direct>
-          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
-            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
-          </direct>
-          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
-            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
-          </direct>
-          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
-            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
-          </direct>
-          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
-            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
-          </direct>
-          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
-            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-    </pb_type>
-    <!-- Define single-mode dual-port memory end -->
-  </complexblocklist>
-</architecture>

openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml

@@ -1,742 +0,0 @@
-<!-- 
-  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
-    with optionally registered outputs
-    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
-    Carry chain links to vertically adjacent logic blocks
-  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
-    Height = 6, found on every (8n+2)th column
-  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
-    Height = 4, found on every (8n+6)th column
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  The electrical design of the architecture described here is NOT from an 
-  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
-  architecture file by using an existing commercial FPGA to approximate the area, 
-  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
-  model of wiring and circuit design for low-level routing components, where available.
-  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
-  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
-  modified and you will still get reasonable delay results for the new architecture.
-  The following describes, in detail, how we obtained the various electrical values for this 
-  architecture.
-
-  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
-  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
-  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
-  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
-  match the overall target (a 40 nm FPGA).
-
-  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
-  memories, and multipliers from test circuits on a Stratix IV GX device 
-  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
-  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
-  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
-  take the R and C data from the ITRS roadmap.  
-
-  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
-  crossbar is close enough to the crossbar modelled here.  
-  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
-  36:1 multiplexers.  We match these parameters in this architecture.
-
-  For LUTs, we include LUT 
-  delays measured from Stratix IV which is dependant on the input used (ie. some 
-  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
-  not consider differences in LUT input delays.
-
-  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
-  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
-  all pins except clock virtual) then measuring the delays in chip-planner, 
-  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
-  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
-  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
-  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
-  overhead that we don't have, I'll approximate the delay of a simpler chain at 
-  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
-  can be justified).
-
-  Logic block area numbers obtained by scaling overall tile area of a 65nm 
-  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
-  routing area at a channel width of 300. We use a channel width of 300 because it can route 
-  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
-  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
-  choosing a width that provides high routability. The architecture can be routed at different channel
-  widths, but we estimate the tile size and hence the physical length of routing wires assuming
-  a channel width of 300.
-
-  Sanity checks employed:
-    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
-        common electrical design.
-
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--->
-<architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
-  -->
-  <models>
-    <model name="adder">
-      <input_ports>
-        <port name="a" combinational_sink_ports="sumout cout"/>
-        <port name="b" combinational_sink_ports="sumout cout"/>
-        <port name="cin" combinational_sink_ports="sumout cout"/>
-      </input_ports>
-      <output_ports>
-        <port name="cout"/>
-        <port name="sumout"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="io">
-      <input_ports>
-        <port name="outpad"/>
-      </input_ports>
-      <output_ports>
-        <port name="inpad"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="frac_lut6">
-      <input_ports>
-        <port name="in"/>
-      </input_ports>
-      <output_ports>
-        <port name="lut4_out"/>
-        <port name="lut5_out"/>
-        <port name="lut6_out"/>
-      </output_ports>
-    </model>
-    <model name="dual_port_ram">
-      <input_ports>
-        <!-- write address lines -->
-        <port name="waddr" clock="clk"/>
-        <!-- read address lines -->
-        <port name="raddr" clock="clk"/>
-        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
-        <port name="d_in" clock="clk"/>
-        <!-- write enable -->
-        <port name="wen" clock="clk"/>
-        <!-- read enable -->
-        <port name="ren" clock="clk"/>
-        <!-- memories are often clocked -->
-        <port name="clk" is_clock="1"/>
-      </input_ports>
-      <output_ports>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-        <port name="d_out" clock="clk"/>
-      </output_ports>
-    </model>
-  </models>
-  <tiles>
-    <tile name="io" capacity="8" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad</loc>
-        <loc side="top">io.outpad io.inpad</loc>
-        <loc side="right">io.outpad io.inpad</loc>
-        <loc side="bottom">io.outpad io.inpad</loc>
-      </pinlocations>
-    </tile>
-    <tile name="clb" area="53894">
-      <equivalent_sites>
-        <site pb_type="clb"/>
-      </equivalent_sites>
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
-      </fc>
-      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
-      <!--pinlocations pattern="spread"/-->
-      <pinlocations pattern="custom">
-        <loc side="left">clb.clk</loc>
-        <loc side="top">clb.cin</loc>
-        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
-        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
-      </pinlocations>
-    </tile>
-    <tile name="memory" height="2" area="548000">
-      <equivalent_sites>
-        <site pb_type="memory"/>
-      </equivalent_sites>
-      <input name="waddr" num_pins="10"/>
-      <input name="raddr" num_pins="10"/>
-      <input name="d_in" num_pins="32"/>
-      <input name="wen" num_pins="1"/>
-      <input name="ren" num_pins="1"/>
-      <output name="d_out" num_pins="32"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
-  <layout tileable="true" through_channel="false">
-    <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="7" height="6">
-      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
-      <perimeter type="io" priority="10"/>
-      <corners type="EMPTY" priority="101"/>
-      <!--Fill with 'clb'-->
-      <fill type="clb" priority="1"/>
-      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
-      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
-      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-      <row type="EMPTY" starty="H-1" priority="11"/>
-      <row type="EMPTY" starty="0" priority="11"/>
-      <!-- Single instance of an AIB interface -->
-    </fixed_layout>
-    <!-- /auto_layout -->
-  </layout>
-  <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
-    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	    -->
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="wilton" fs="3"/>
-    <connection_block input_switch_name="ipin_cblock"/>
-  </device>
-  <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-           book area formula. This means the mux transistors are about 5x minimum drive strength.
-           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-           2.5x when looking up in Jeff's tables.
-           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
-  </switchlist>
-  <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
-      <mux name="0"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-  </segmentlist>
-  <directlist>
-    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
-  </directlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-
-      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
-           If you need to register the I/O, define clocks in the circuit models
-           These clocks can be handled in back-end
-       -->
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->
-      <mode name="physical" packable="false">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
-          </direct>
-          <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-      <power method="ignore"/>
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
-    <pb_type name="clb">
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Describe fracturable logic element.  
-             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
-             The outputs of the fracturable logic element can be optionally registered
-        -->
-      <pb_type name="fle" num_pb="10">
-        <input name="in" num_pins="6"/>
-        <input name="cin" num_pins="1"/>
-        <output name="out" num_pins="2"/>
-        <output name="cout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" packable="false">
-          <pb_type name="fabric" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="2"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="frac_logic" num_pb="1">
-              <input name="in" num_pins="6"/>
-              <output name="lut4_out" num_pins="4"/>
-              <output name="out" num_pins="2"/>
-              <!-- Define LUT -->
-              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
-                <input name="in" num_pins="6"/>
-                <output name="lut4_out" num_pins="4"/>
-                <output name="lut5_out" num_pins="2"/>
-                <output name="lut6_out" num_pins="1"/>
-              </pb_type>
-              <interconnect>
-                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
-                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
-                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
-                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
-                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
-              </interconnect>
-            </pb_type>
-            <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>         
-            <!-- Define adders -->
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
-                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
-              </mux>
-              <mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
-                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
-              </mux>
-              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
-                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
-              </mux>
-              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
-                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="fabric.in"/>
-            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
-            <direct name="direct3" input="fabric.out" output="fle.out"/>
-            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
-            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Physical mode definition end (physical implementation of the fle) -->
-        <!-- BEGIN fle mode of dual lut5 -->
-        <mode name="n2_lut5">
-          <pb_type name="ble5" num_pb="2">
-            <input name="in" num_pins="5"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Regular LUT mode -->
-            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="5" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                  we instead take the average of these numbers to get more stable results
-                82e-12
-                173e-12
-                261e-12
-                263e-12
-                398e-12
-                -->
-              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-              </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble5.in" output="lut5.in"/>
-              <direct name="direct2" input="lut5.out" output="ff.D">
-                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
-                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
-            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
-            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
-            <direct name="direct4" input="ble5.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- END fle mode of dual lut5 -->
-        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
-        <mode name="arithmetic">
-          <pb_type name="arithmetic" num_pb="2">
-            <input name="in" num_pins="4"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="1"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Special dual-LUT mode that drives adder only -->
-            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
-              <input name="in" num_pins="4" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  -->
-              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                  195e-12
-                  195e-12
-                  195e-12
-                  195e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
-              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
-              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
-              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
-                </direct>
-              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
-                </direct>
-              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
-                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
-              </direct>
-              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
-                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
-              </direct>
-              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
-                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
-              </direct>
-              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
-                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
-            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
-            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
-              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
-            </direct>
-            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
-              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
-            </direct>
-            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
-              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
-            </direct>
-            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
-            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- n2_lut5 -->
-        <mode name="n1_lut6">
-          <pb_type name="ble6" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="6" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
-              <direct name="direct2" input="lut6.out" output="ff.D">
-                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
-            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
-            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
-          </interconnect>
-        </mode>
-        <!-- n1_lut6 -->
-      </pb_type>
-      <interconnect>
-        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
-           The delays below come from Stratix IV. the delay through a connection block
-           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-           delay within the crossbar is 95 ps. 
-           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-           to get the part that should be marked on the crossbar.	 -->
-        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
-          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
-          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
-        </complete>
-
-        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-        </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-                 naive specification).
-          -->
-        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
-        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
-        <!-- Carry chain links -->
-        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
-          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
-        </direct>
-        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
-          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
-        </direct>
-        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
-          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
-        </direct>
-      </interconnect>
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-    <!-- Define single-mode dual-port memory begin -->
-    <pb_type name="memory">
-      <input name="waddr" num_pins="10"/>
-      <input name="raddr" num_pins="10"/>
-      <input name="d_in" num_pins="32"/>
-      <input name="wen" num_pins="1"/>
-      <input name="ren" num_pins="1"/>
-      <output name="d_out" num_pins="32"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Specify the 512x32=16Kbit memory block
-           Note: the delay numbers are extracted from VPR flagship XML without modification
-                 Should align to the process technology we using to create the 16K dual-port RAM
-        -->
-      <mode name="mem_512x32_dp">
-        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="waddr" num_pins="10" port_class="address"/>
-          <input name="raddr" num_pins="10" port_class="address"/>
-          <input name="d_in" num_pins="32" port_class="data_in"/>
-          <input name="wen" num_pins="1" port_class="write_en"/>
-          <input name="ren" num_pins="1" port_class="write_en"/>
-          <output name="d_out" num_pins="32" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="17.9e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
-            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
-          </direct>
-          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
-            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
-          </direct>
-          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
-            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
-          </direct>
-          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
-            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
-          </direct>
-          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
-            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
-          </direct>
-          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
-            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-    </pb_type>
-    <!-- Define single-mode dual-port memory end -->
-  </complexblocklist>
-</architecture>

openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml

@@ -1,739 +0,0 @@
-<!-- 
-  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
-    with optionally registered outputs
-    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
-    Carry chain links to vertically adjacent logic blocks
-  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
-    Height = 6, found on every (8n+2)th column
-  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
-    Height = 4, found on every (8n+6)th column
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  The electrical design of the architecture described here is NOT from an 
-  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
-  architecture file by using an existing commercial FPGA to approximate the area, 
-  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
-  model of wiring and circuit design for low-level routing components, where available.
-  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
-  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
-  modified and you will still get reasonable delay results for the new architecture.
-  The following describes, in detail, how we obtained the various electrical values for this 
-  architecture.
-
-  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
-  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
-  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
-  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
-  match the overall target (a 40 nm FPGA).
-
-  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
-  memories, and multipliers from test circuits on a Stratix IV GX device 
-  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
-  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
-  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
-  take the R and C data from the ITRS roadmap.  
-
-  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
-  crossbar is close enough to the crossbar modelled here.  
-  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
-  36:1 multiplexers.  We match these parameters in this architecture.
-
-  For LUTs, we include LUT 
-  delays measured from Stratix IV which is dependant on the input used (ie. some 
-  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
-  not consider differences in LUT input delays.
-
-  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
-  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
-  all pins except clock virtual) then measuring the delays in chip-planner, 
-  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
-  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
-  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
-  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
-  overhead that we don't have, I'll approximate the delay of a simpler chain at 
-  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
-  can be justified).
-
-  Logic block area numbers obtained by scaling overall tile area of a 65nm 
-  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
-  routing area at a channel width of 300. We use a channel width of 300 because it can route 
-  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
-  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
-  choosing a width that provides high routability. The architecture can be routed at different channel
-  widths, but we estimate the tile size and hence the physical length of routing wires assuming
-  a channel width of 300.
-
-  Sanity checks employed:
-    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
-        common electrical design.
-
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--->
-<architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
-  -->
-  <models>
-    <model name="adder">
-      <input_ports>
-        <port name="a" combinational_sink_ports="sumout cout"/>
-        <port name="b" combinational_sink_ports="sumout cout"/>
-        <port name="cin" combinational_sink_ports="sumout cout"/>
-      </input_ports>
-      <output_ports>
-        <port name="cout"/>
-        <port name="sumout"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="io">
-      <input_ports>
-        <port name="outpad"/>
-      </input_ports>
-      <output_ports>
-        <port name="inpad"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="frac_lut6">
-      <input_ports>
-        <port name="in"/>
-      </input_ports>
-      <output_ports>
-        <port name="lut4_out"/>
-        <port name="lut5_out"/>
-        <port name="lut6_out"/>
-      </output_ports>
-    </model>
-    <model name="dual_port_ram">
-      <input_ports>
-        <!-- write address lines -->
-        <port name="waddr" clock="clk"/>
-        <!-- read address lines -->
-        <port name="raddr" clock="clk"/>
-        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
-        <port name="d_in" clock="clk"/>
-        <!-- write enable -->
-        <port name="wen" clock="clk"/>
-        <!-- read enable -->
-        <port name="ren" clock="clk"/>
-        <!-- memories are often clocked -->
-        <port name="clk" is_clock="1"/>
-      </input_ports>
-      <output_ports>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-        <port name="d_out" clock="clk"/>
-      </output_ports>
-    </model>
-  </models>
-  <tiles>
-    <tile name="io" capacity="8" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad</loc>
-        <loc side="top">io.outpad io.inpad</loc>
-        <loc side="right">io.outpad io.inpad</loc>
-        <loc side="bottom">io.outpad io.inpad</loc>
-      </pinlocations>
-    </tile>
-    <tile name="clb" area="53894">
-      <equivalent_sites>
-        <site pb_type="clb"/>
-      </equivalent_sites>
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
-      </fc>
-      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
-      <!--pinlocations pattern="spread"/-->
-      <pinlocations pattern="custom">
-        <loc side="left">clb.clk</loc>
-        <loc side="top">clb.cin</loc>
-        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
-        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
-      </pinlocations>
-    </tile>
-    <tile name="memory" width="2" height="2" area="548000">
-      <equivalent_sites>
-        <site pb_type="memory"/>
-      </equivalent_sites>
-      <input name="waddr" num_pins="10"/>
-      <input name="raddr" num_pins="10"/>
-      <input name="d_in" num_pins="32"/>
-      <input name="wen" num_pins="1"/>
-      <input name="ren" num_pins="1"/>
-      <output name="d_out" num_pins="32"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
-  <layout tileable="true" through_channel="false">
-    <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="6" height="6">
-      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
-      <perimeter type="io" priority="100"/>
-      <corners type="EMPTY" priority="101"/>
-      <!--Fill with 'clb'-->
-      <fill type="clb" priority="10"/>
-      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
-      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
-      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-    </fixed_layout>
-    <!-- /auto_layout -->
-  </layout>
-  <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
-    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	    -->
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="wilton" fs="3"/>
-    <connection_block input_switch_name="ipin_cblock"/>
-  </device>
-  <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-           book area formula. This means the mux transistors are about 5x minimum drive strength.
-           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-           2.5x when looking up in Jeff's tables.
-           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
-  </switchlist>
-  <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
-      <mux name="0"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-  </segmentlist>
-  <directlist>
-    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
-  </directlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-
-      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
-           If you need to register the I/O, define clocks in the circuit models
-           These clocks can be handled in back-end
-       -->
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->
-      <mode name="physical" packable="false">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
-          </direct>
-          <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-      <power method="ignore"/>
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
-    <pb_type name="clb">
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Describe fracturable logic element.  
-             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
-             The outputs of the fracturable logic element can be optionally registered
-        -->
-      <pb_type name="fle" num_pb="10">
-        <input name="in" num_pins="6"/>
-        <input name="cin" num_pins="1"/>
-        <output name="out" num_pins="2"/>
-        <output name="cout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" packable="false">
-          <pb_type name="fabric" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="2"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="frac_logic" num_pb="1">
-              <input name="in" num_pins="6"/>
-              <output name="lut4_out" num_pins="4"/>
-              <output name="out" num_pins="2"/>
-              <!-- Define LUT -->
-              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
-                <input name="in" num_pins="6"/>
-                <output name="lut4_out" num_pins="4"/>
-                <output name="lut5_out" num_pins="2"/>
-                <output name="lut6_out" num_pins="1"/>
-              </pb_type>
-              <interconnect>
-                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
-                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
-                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
-                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
-                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
-              </interconnect>
-            </pb_type>
-            <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>         
-            <!-- Define adders -->
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout frac_logic.out[0]" output="ff[0].D">
-                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0]" out_port="ff[0].D"/>
-              </mux>
-              <mux name="mux2" input="adder[1].sumout frac_logic.out[1]" output="ff[1].D">
-                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1]" out_port="ff[1].D"/>
-              </mux>
-              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
-                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
-              </mux>
-              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
-                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="fabric.in"/>
-            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
-            <direct name="direct3" input="fabric.out" output="fle.out"/>
-            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
-            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Physical mode definition end (physical implementation of the fle) -->
-        <!-- BEGIN fle mode of dual lut5 -->
-        <mode name="n2_lut5">
-          <pb_type name="ble5" num_pb="2">
-            <input name="in" num_pins="5"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Regular LUT mode -->
-            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="5" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                  we instead take the average of these numbers to get more stable results
-                82e-12
-                173e-12
-                261e-12
-                263e-12
-                398e-12
-                -->
-              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-              </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble5.in" output="lut5.in"/>
-              <direct name="direct2" input="lut5.out" output="ff.D">
-                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
-                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
-            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
-            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
-            <direct name="direct4" input="ble5.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- END fle mode of dual lut5 -->
-        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
-        <mode name="arithmetic">
-          <pb_type name="arithmetic" num_pb="2">
-            <input name="in" num_pins="4"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="1"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Special dual-LUT mode that drives adder only -->
-            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
-              <input name="in" num_pins="4" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  -->
-              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                  195e-12
-                  195e-12
-                  195e-12
-                  195e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
-              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
-              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
-              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
-                </direct>
-              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
-                </direct>
-              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
-                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
-              </direct>
-              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
-                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
-              </direct>
-              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
-                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
-              </direct>
-              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
-                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
-            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
-            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
-              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
-            </direct>
-            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
-              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
-            </direct>
-            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
-              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
-            </direct>
-            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
-            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- n2_lut5 -->
-        <mode name="n1_lut6">
-          <pb_type name="ble6" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="6" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
-              <direct name="direct2" input="lut6.out" output="ff.D">
-                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
-            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
-            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
-          </interconnect>
-        </mode>
-        <!-- n1_lut6 -->
-      </pb_type>
-      <interconnect>
-        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
-           The delays below come from Stratix IV. the delay through a connection block
-           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-           delay within the crossbar is 95 ps. 
-           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-           to get the part that should be marked on the crossbar.	 -->
-        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
-          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
-          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
-        </complete>
-
-        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-        </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-                 naive specification).
-          -->
-        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
-        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
-        <!-- Carry chain links -->
-        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
-          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
-        </direct>
-        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
-          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
-        </direct>
-        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
-          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
-        </direct>
-      </interconnect>
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-    <!-- Define single-mode dual-port memory begin -->
-    <pb_type name="memory">
-      <input name="waddr" num_pins="10"/>
-      <input name="raddr" num_pins="10"/>
-      <input name="d_in" num_pins="32"/>
-      <input name="wen" num_pins="1"/>
-      <input name="ren" num_pins="1"/>
-      <output name="d_out" num_pins="32"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Specify the 512x32=16Kbit memory block
-           Note: the delay numbers are extracted from VPR flagship XML without modification
-                 Should align to the process technology we using to create the 16K dual-port RAM
-        -->
-      <mode name="mem_512x32_dp">
-        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="waddr" num_pins="10" port_class="address"/>
-          <input name="raddr" num_pins="10" port_class="address"/>
-          <input name="d_in" num_pins="32" port_class="data_in"/>
-          <input name="wen" num_pins="1" port_class="write_en"/>
-          <input name="ren" num_pins="1" port_class="write_en"/>
-          <output name="d_out" num_pins="32" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="17.9e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
-            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
-          </direct>
-          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
-            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
-          </direct>
-          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
-            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
-          </direct>
-          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
-            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
-          </direct>
-          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
-            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
-          </direct>
-          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
-            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-    </pb_type>
-    <!-- Define single-mode dual-port memory end -->
-  </complexblocklist>
-</architecture>

openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml

@@ -1,696 +0,0 @@
-<!-- 
-  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
-    with optionally registered outputs
-    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
-    Carry chain links to vertically adjacent logic blocks
-  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
-    Height = 6, found on every (8n+2)th column
-  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
-    Height = 4, found on every (8n+6)th column
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  The electrical design of the architecture described here is NOT from an 
-  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
-  architecture file by using an existing commercial FPGA to approximate the area, 
-  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
-  model of wiring and circuit design for low-level routing components, where available.
-  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
-  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
-  modified and you will still get reasonable delay results for the new architecture.
-  The following describes, in detail, how we obtained the various electrical values for this 
-  architecture.
-
-  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
-  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
-  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
-  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
-  match the overall target (a 40 nm FPGA).
-
-  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
-  memories, and multipliers from test circuits on a Stratix IV GX device 
-  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
-  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
-  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
-  take the R and C data from the ITRS roadmap.  
-
-  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
-  crossbar is close enough to the crossbar modelled here.  
-  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
-  36:1 multiplexers.  We match these parameters in this architecture.
-
-  For LUTs, we include LUT 
-  delays measured from Stratix IV which is dependant on the input used (ie. some 
-  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
-  not consider differences in LUT input delays.
-
-  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
-  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
-  all pins except clock virtual) then measuring the delays in chip-planner, 
-  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
-  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
-  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
-  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
-  overhead that we don't have, I'll approximate the delay of a simpler chain at 
-  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
-  can be justified).
-
-  Logic block area numbers obtained by scaling overall tile area of a 65nm 
-  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
-  routing area at a channel width of 300. We use a channel width of 300 because it can route 
-  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
-  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
-  choosing a width that provides high routability. The architecture can be routed at different channel
-  widths, but we estimate the tile size and hence the physical length of routing wires assuming
-  a channel width of 300.
-
-  Sanity checks employed:
-    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
-        common electrical design.
-
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--->
-<architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
-  -->
-  <models>
-    <model name="adder">
-      <input_ports>
-        <port name="a" combinational_sink_ports="sumout cout"/>
-        <port name="b" combinational_sink_ports="sumout cout"/>
-        <port name="cin" combinational_sink_ports="sumout cout"/>
-      </input_ports>
-      <output_ports>
-        <port name="cout"/>
-        <port name="sumout"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="io">
-      <input_ports>
-        <port name="outpad"/>
-      </input_ports>
-      <output_ports>
-        <port name="inpad"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="frac_lut6">
-      <input_ports>
-        <port name="in"/>
-      </input_ports>
-      <output_ports>
-        <port name="lut4_out"/>
-        <port name="lut5_out"/>
-        <port name="lut6_out"/>
-      </output_ports>
-    </model>
-  </models>
-  <tiles>
-    <tile name="io" capacity="8" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad</loc>
-        <loc side="top">io.outpad io.inpad</loc>
-        <loc side="right">io.outpad io.inpad</loc>
-        <loc side="bottom">io.outpad io.inpad</loc>
-      </pinlocations>
-    </tile>
-    <tile name="clb" area="53894">
-      <equivalent_sites>
-        <site pb_type="clb"/>
-      </equivalent_sites>
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <input name="regin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <output name="regout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="regin" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="regout" fc_type="frac" fc_val="0"/>
-      </fc>
-      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
-      <!--pinlocations pattern="spread"/-->
-      <pinlocations pattern="custom">
-        <loc side="left">clb.clk</loc>
-        <loc side="top">clb.cin clb.regin</loc>
-        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
-        <loc side="bottom">clb.cout clb.regout clb.O[19:10] clb.I[39:20]</loc>
-      </pinlocations>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
-  <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="6" height="6">
-      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
-      <perimeter type="io" priority="100"/>
-      <corners type="EMPTY" priority="101"/>
-      <!--Fill with 'clb'-->
-      <fill type="clb" priority="10"/>
-    </fixed_layout>
-    <!-- /auto_layout -->
-  </layout>
-  <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
-    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	    -->
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="wilton" fs="3"/>
-    <connection_block input_switch_name="ipin_cblock"/>
-  </device>
-  <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-           book area formula. This means the mux transistors are about 5x minimum drive strength.
-           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-           2.5x when looking up in Jeff's tables.
-           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
-  </switchlist>
-  <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
-      <mux name="0"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-  </segmentlist>
-  <directlist>
-    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
-    <direct name="shift_register" from_pin="clb.regout" to_pin="clb.regin" x_offset="0" y_offset="-1" z_offset="0"/>
-  </directlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-
-      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
-           If you need to register the I/O, define clocks in the circuit models
-           These clocks can be handled in back-end
-       -->
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->
-      <mode name="physical" packable="false">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
-          </direct>
-          <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-      <power method="ignore"/>
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
-    <pb_type name="clb">
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <input name="regin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <output name="regout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Describe fracturable logic element.  
-             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
-             The outputs of the fracturable logic element can be optionally registered
-        -->
-      <pb_type name="fle" num_pb="10">
-        <input name="in" num_pins="6"/>
-        <input name="cin" num_pins="1"/>
-        <input name="regin" num_pins="1"/>
-        <output name="out" num_pins="2"/>
-        <output name="cout" num_pins="1"/>
-        <output name="regout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" packable="false">
-          <pb_type name="fabric" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <input name="cin" num_pins="1"/>
-            <input name="regin" num_pins="1"/>
-            <output name="out" num_pins="2"/>
-            <output name="cout" num_pins="1"/>
-            <output name="regout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="frac_logic" num_pb="1">
-              <input name="in" num_pins="6"/>
-              <output name="lut4_out" num_pins="4"/>
-              <output name="out" num_pins="2"/>
-              <!-- Define LUT -->
-              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
-                <input name="in" num_pins="6"/>
-                <output name="lut4_out" num_pins="4"/>
-                <output name="lut5_out" num_pins="2"/>
-                <output name="lut6_out" num_pins="1"/>
-              </pb_type>
-              <interconnect>
-                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
-                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
-                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
-                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
-                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
-              </interconnect>
-            </pb_type>
-            <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>         
-            <!-- Define adders -->
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout frac_logic.out[0] fabric.regin" output="ff[0].D">
-                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0] fabric.regin" out_port="ff[0].D"/>
-              </mux>
-              <mux name="mux2" input="adder[1].sumout frac_logic.out[1] ff[0].Q" output="ff[1].D">
-                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1] ff[0].Q" out_port="ff[1].D"/>
-              </mux>
-              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
-                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
-              </mux>
-              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
-                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="fabric.in"/>
-            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
-            <direct name="direct3" input="fle.regin" output="fabric.regin"/>
-            <direct name="direct4" input="fabric.out" output="fle.out"/>
-            <direct name="direct5" input="fabric.cout" output="fle.cout"/>
-            <direct name="direct6" input="fabric.regout" output="fle.regout"/>
-            <direct name="direct7" input="fle.clk" output="fabric.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Physical mode definition end (physical implementation of the fle) -->
-        <!-- BEGIN fle mode of dual lut5 -->
-        <mode name="n2_lut5">
-          <pb_type name="ble5" num_pb="2">
-            <input name="in" num_pins="5"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Regular LUT mode -->
-            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="5" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                  we instead take the average of these numbers to get more stable results
-                82e-12
-                173e-12
-                261e-12
-                263e-12
-                398e-12
-                -->
-              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-              </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble5.in" output="lut5.in"/>
-              <direct name="direct2" input="lut5.out" output="ff.D">
-                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
-                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
-            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
-            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
-            <direct name="direct4" input="ble5.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- END fle mode of dual lut5 -->
-        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
-        <mode name="arithmetic">
-          <pb_type name="arithmetic" num_pb="2">
-            <input name="in" num_pins="4"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="1"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Special dual-LUT mode that drives adder only -->
-            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
-              <input name="in" num_pins="4" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  -->
-              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                  195e-12
-                  195e-12
-                  195e-12
-                  195e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
-              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
-              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
-              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
-                </direct>
-              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
-                </direct>
-              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
-                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
-              </direct>
-              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
-                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
-              </direct>
-              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
-                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
-              </direct>
-              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
-                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
-            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
-            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
-              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
-            </direct>
-            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
-              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
-            </direct>
-            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
-              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
-            </direct>
-            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
-            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- n2_lut5 -->
-        <mode name="n1_lut6">
-          <pb_type name="ble6" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="6" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
-              <direct name="direct2" input="lut6.out" output="ff.D">
-                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
-            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
-            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Define n1_lut6 end -->
-        <!-- Define shift register begin -->
-        <mode name="shift_register">
-          <pb_type name="shift_reg" num_pb="1">
-            <input name="regin" num_pins="1"/>
-            <output name="regout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="shift_reg.regin" output="ff[0].D"/>
-              <direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
-              <direct name="direct3" input="ff[1].Q" output="shift_reg.regout"/>
-              <complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.regin" output="shift_reg.regin"/>
-            <direct name="direct2" input="shift_reg.regout" output="fle.regout"/>
-            <direct name="direct3" input="fle.clk" output="shift_reg.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Define shift register end --> 
-      </pb_type>
-      <interconnect>
-        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
-           The delays below come from Stratix IV. the delay through a connection block
-           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-           delay within the crossbar is 95 ps. 
-           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-           to get the part that should be marked on the crossbar.	 -->
-        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
-          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
-          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
-        </complete>
-
-        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-        </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-                 naive specification).
-          -->
-        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
-        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
-        <!-- Carry chain links -->
-        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
-          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
-        </direct>
-        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
-          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
-        </direct>
-        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
-          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
-        </direct>
-        <!-- Shift register chain links -->
-        <direct name="shift_register_in" input="clb.regin" output="fle[0:0].regin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
-          <pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/>
-        </direct>
-        <direct name="shift_register_out" input="fle[9:9].regout" output="clb.regout">
-          <pack_pattern name="chain" in_port="fle[9:9].regout" out_port="clb.regout"/>
-        </direct>
-        <direct name="shift_register_link" input="fle[8:0].regout" output="fle[9:1].regin">
-          <pack_pattern name="chain" in_port="fle[8:0].regout" out_port="fle[9:1].regin"/>
-        </direct>
-      </interconnect>
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-  </complexblocklist>
-</architecture>

openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml

@@ -1,734 +0,0 @@
-<!-- 
-  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
-    with optionally registered outputs
-    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
-    Carry chain links to vertically adjacent logic blocks
-  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
-    Height = 6, found on every (8n+2)th column
-  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
-    Height = 4, found on every (8n+6)th column
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  The electrical design of the architecture described here is NOT from an 
-  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
-  architecture file by using an existing commercial FPGA to approximate the area, 
-  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
-  model of wiring and circuit design for low-level routing components, where available.
-  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
-  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
-  modified and you will still get reasonable delay results for the new architecture.
-  The following describes, in detail, how we obtained the various electrical values for this 
-  architecture.
-
-  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
-  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
-  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
-  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
-  match the overall target (a 40 nm FPGA).
-
-  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
-  memories, and multipliers from test circuits on a Stratix IV GX device 
-  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
-  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
-  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
-  take the R and C data from the ITRS roadmap.  
-
-  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
-  crossbar is close enough to the crossbar modelled here.  
-  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
-  36:1 multiplexers.  We match these parameters in this architecture.
-
-  For LUTs, we include LUT 
-  delays measured from Stratix IV which is dependant on the input used (ie. some 
-  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
-  not consider differences in LUT input delays.
-
-  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
-  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
-  all pins except clock virtual) then measuring the delays in chip-planner, 
-  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
-  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
-  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
-  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
-  overhead that we don't have, I'll approximate the delay of a simpler chain at 
-  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
-  can be justified).
-
-  Logic block area numbers obtained by scaling overall tile area of a 65nm 
-  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
-  routing area at a channel width of 300. We use a channel width of 300 because it can route 
-  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
-  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
-  choosing a width that provides high routability. The architecture can be routed at different channel
-  widths, but we estimate the tile size and hence the physical length of routing wires assuming
-  a channel width of 300.
-
-  Sanity checks employed:
-    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
-        common electrical design.
-
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--->
-<architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
-  -->
-  <models>
-    <model name="adder">
-      <input_ports>
-        <port name="a" combinational_sink_ports="sumout cout"/>
-        <port name="b" combinational_sink_ports="sumout cout"/>
-        <port name="cin" combinational_sink_ports="sumout cout"/>
-      </input_ports>
-      <output_ports>
-        <port name="cout"/>
-        <port name="sumout"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="io">
-      <input_ports>
-        <port name="outpad"/>
-      </input_ports>
-      <output_ports>
-        <port name="inpad"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for fractruable LUT to be used in the physical mode of LUT -->
-    <model name="frac_lut6">
-      <input_ports>
-        <port name="in"/>
-      </input_ports>
-      <output_ports>
-        <port name="lut4_out"/>
-        <port name="lut5_out"/>
-        <port name="lut6_out"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for scan-chain flip-flop to be used in the physical mode of FF -->
-    <model name="scff">
-      <input_ports>
-        <port name="D" clock="clk"/>
-        <port name="DI" clock="clk"/>
-        <port name="clk" is_clock="1"/>
-      </input_ports>
-      <output_ports>
-        <port name="Q" clock="clk"/>
-      </output_ports>
-    </model>
-  </models>
-  <tiles>
-    <tile name="io" capacity="8" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad</loc>
-        <loc side="top">io.outpad io.inpad</loc>
-        <loc side="right">io.outpad io.inpad</loc>
-        <loc side="bottom">io.outpad io.inpad</loc>
-      </pinlocations>
-    </tile>
-    <tile name="clb" area="53894">
-      <equivalent_sites>
-        <site pb_type="clb"/>
-      </equivalent_sites>
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <input name="regin" num_pins="1"/>
-      <input name="scin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <output name="regout" num_pins="1"/>
-      <output name="scout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="regin" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="regout" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="scin" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="scout" fc_type="frac" fc_val="0"/>
-      </fc>
-      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
-      <!--pinlocations pattern="spread"/-->
-      <pinlocations pattern="custom">
-        <loc side="left">clb.clk</loc>
-        <loc side="top">clb.cin clb.regin clb.scin</loc>
-        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
-        <loc side="bottom">clb.cout clb.regout clb.scout clb.O[19:10] clb.I[39:20]</loc>
-      </pinlocations>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
-  <layout tileable="true">
-    <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="6" height="6">
-      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
-      <perimeter type="io" priority="100"/>
-      <corners type="EMPTY" priority="101"/>
-      <!--Fill with 'clb'-->
-      <fill type="clb" priority="10"/>
-    </fixed_layout>
-    <!-- /auto_layout -->
-  </layout>
-  <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
-    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	    -->
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="wilton" fs="3"/>
-    <connection_block input_switch_name="ipin_cblock"/>
-  </device>
-  <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-           book area formula. This means the mux transistors are about 5x minimum drive strength.
-           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-           2.5x when looking up in Jeff's tables.
-           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
-  </switchlist>
-  <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
-      <mux name="0"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-  </segmentlist>
-  <directlist>
-    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
-    <direct name="shift_register" from_pin="clb.regout" to_pin="clb.regin" x_offset="0" y_offset="-1" z_offset="0"/>
-    <direct name="scan_chain" from_pin="clb.scout" to_pin="clb.scin" x_offset="0" y_offset="-1" z_offset="0"/>
-  </directlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-
-      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
-           If you need to register the I/O, define clocks in the circuit models
-           These clocks can be handled in back-end
-       -->
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->
-      <mode name="physical" packable="false">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
-          </direct>
-          <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-      <power method="ignore"/>
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
-    <pb_type name="clb">
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <input name="regin" num_pins="1"/>
-      <input name="scin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <output name="regout" num_pins="1"/>
-      <output name="scout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Describe fracturable logic element.  
-             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
-             The outputs of the fracturable logic element can be optionally registered
-        -->
-      <pb_type name="fle" num_pb="10">
-        <input name="in" num_pins="6"/>
-        <input name="cin" num_pins="1"/>
-        <input name="regin" num_pins="1"/>
-        <input name="scin" num_pins="1"/>
-        <output name="out" num_pins="2"/>
-        <output name="cout" num_pins="1"/>
-        <output name="regout" num_pins="1"/>
-        <output name="scout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" packable="false">
-          <pb_type name="fabric" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <input name="cin" num_pins="1"/>
-            <input name="regin" num_pins="1"/>
-            <input name="scin" num_pins="1"/>
-            <output name="out" num_pins="2"/>
-            <output name="cout" num_pins="1"/>
-            <output name="regout" num_pins="1"/>
-            <output name="scout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="frac_logic" num_pb="1">
-              <input name="in" num_pins="6"/>
-              <output name="lut4_out" num_pins="4"/>
-              <output name="out" num_pins="2"/>
-              <!-- Define LUT -->
-              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
-                <input name="in" num_pins="6"/>
-                <output name="lut4_out" num_pins="4"/>
-                <output name="lut5_out" num_pins="2"/>
-                <output name="lut6_out" num_pins="1"/>
-              </pb_type>
-              <interconnect>
-                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
-                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
-                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
-                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
-                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
-              </interconnect>
-            </pb_type>
-            <!-- Define flip-flop with scan-chain capability, DI is the scan-chain data input -->
-            <pb_type name="ff" blif_model=".subckt scff" num_pb="2">
-              <input name="D" num_pins="1"/>
-              <input name="DI" num_pins="1"/>
-              <output name="Q" num_pins="1"/>
-              <clock name="clk" num_pins="1"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_setup value="66e-12" port="ff.DI" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>         
-            <!-- Define adders -->
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct3" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct4" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct5" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct6" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct7" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct8" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <direct name="direct9" input="fabric.scin" output="ff[0].DI"/>
-              <direct name="direct10" input="ff[0].Q" output="ff[1].DI"/>
-              <direct name="direct11" input="ff[1].Q" output="fabric.scout"/>
-              <complete name="complete1" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout frac_logic.out[0] fabric.regin" output="ff[0].D">
-                <delay_constant max="25e-12" in_port="adder[0].sumout frac_logic.out[0] fabric.regin" out_port="ff[0].D"/>
-              </mux>
-              <mux name="mux2" input="adder[1].sumout frac_logic.out[1] ff[0].Q" output="ff[1].D">
-                <delay_constant max="25e-12" in_port="adder[1].sumout frac_logic.out[1] ff[0].Q" out_port="ff[1].D"/>
-              </mux>
-              <mux name="mux3" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
-                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
-              </mux>
-              <mux name="mux4" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
-                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="fabric.in"/>
-            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
-            <direct name="direct3" input="fle.regin" output="fabric.regin"/>
-            <direct name="direct4" input="fle.scin" output="fabric.scin"/>
-            <direct name="direct5" input="fabric.out" output="fle.out"/>
-            <direct name="direct6" input="fabric.cout" output="fle.cout"/>
-            <direct name="direct7" input="fabric.regout" output="fle.regout"/>
-            <direct name="direct8" input="fabric.scout" output="fle.scout"/>
-            <direct name="direct9" input="fle.clk" output="fabric.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Physical mode definition end (physical implementation of the fle) -->
-        <!-- BEGIN fle mode of dual lut5 -->
-        <mode name="n2_lut5">
-          <pb_type name="ble5" num_pb="2">
-            <input name="in" num_pins="5"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Regular LUT mode -->
-            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="5" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                  we instead take the average of these numbers to get more stable results
-                82e-12
-                173e-12
-                261e-12
-                263e-12
-                398e-12
-                -->
-              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-              </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble5.in" output="lut5.in"/>
-              <direct name="direct2" input="lut5.out" output="ff.D">
-                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
-                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
-            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
-            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
-            <direct name="direct4" input="ble5.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- END fle mode of dual lut5 -->
-        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
-        <mode name="arithmetic">
-          <pb_type name="arithmetic" num_pb="2">
-            <input name="in" num_pins="4"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="1"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Special dual-LUT mode that drives adder only -->
-            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
-              <input name="in" num_pins="4" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  -->
-              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                  195e-12
-                  195e-12
-                  195e-12
-                  195e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
-              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
-              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
-              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
-                </direct>
-              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
-                </direct>
-              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
-                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
-              </direct>
-              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
-                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
-              </direct>
-              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
-                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
-              </direct>
-              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
-                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
-            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
-            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
-              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
-            </direct>
-            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
-              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
-            </direct>
-            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
-              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
-            </direct>
-            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
-            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- n2_lut5 -->
-        <mode name="n1_lut6">
-          <pb_type name="ble6" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="6" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
-              <direct name="direct2" input="lut6.out" output="ff.D">
-                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
-            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
-            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Define n1_lut6 end -->
-        <!-- Define shift register begin -->
-        <mode name="shift_register">
-          <pb_type name="shift_reg" num_pb="1">
-            <input name="regin" num_pins="1"/>
-            <output name="regout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="shift_reg.regin" output="ff[0].D"/>
-              <direct name="direct2" input="ff[0].Q" output="ff[1].D"/>
-              <direct name="direct3" input="ff[1].Q" output="shift_reg.regout"/>
-              <complete name="complete1" input="shift_reg.clk" output="ff.clk"/>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.regin" output="shift_reg.regin"/>
-            <direct name="direct2" input="shift_reg.regout" output="fle.regout"/>
-            <direct name="direct3" input="fle.clk" output="shift_reg.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Define shift register end --> 
-      </pb_type>
-      <interconnect>
-        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
-           The delays below come from Stratix IV. the delay through a connection block
-           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-           delay within the crossbar is 95 ps. 
-           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-           to get the part that should be marked on the crossbar.	 -->
-        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
-          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
-          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
-        </complete>
-
-        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-        </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-                 naive specification).
-          -->
-        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
-        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
-        <!-- Carry chain links -->
-        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
-          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
-        </direct>
-        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
-          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
-        </direct>
-        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
-          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
-        </direct>
-        <!-- Shift register chain links -->
-        <direct name="shift_register_in" input="clb.regin" output="fle[0:0].regin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.regin" out_port="fle[0:0].regin"/>
-          <pack_pattern name="chain" in_port="clb.regin" out_port="fle[0:0].regin"/>
-        </direct>
-        <direct name="shift_register_out" input="fle[9:9].regout" output="clb.regout">
-          <pack_pattern name="chain" in_port="fle[9:9].regout" out_port="clb.regout"/>
-        </direct>
-        <direct name="shift_register_link" input="fle[8:0].regout" output="fle[9:1].regin">
-          <pack_pattern name="chain" in_port="fle[8:0].regout" out_port="fle[9:1].regin"/>
-        </direct>
-        <!-- Scan chain links -->
-        <direct name="scan_chain_in" input="clb.scin" output="fle[0:0].scin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.scin" out_port="fle[0:0].scin"/>
-        </direct>
-        <direct name="scan_chain_out" input="fle[9:9].scout" output="clb.scout">
-        </direct>
-        <direct name="scan_chain_link" input="fle[8:0].scout" output="fle[9:1].scin">
-        </direct>
-      </interconnect>
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-  </complexblocklist>
-</architecture>

openfpga/test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml

@@ -1,734 +0,0 @@
-<!-- 
-  Flagship Heterogeneous Architecture with Carry Chains for VTR 7.0.
-
-  - 40 nm technology
-  - General purpose logic block: 
-    K = 6, N = 10, fracturable 6 LUTs (can operate as one 6-LUT or two 5-LUTs with 8 total FLE inputs (2 inputs of which are shared by the 5-LUTs) 
-    with optionally registered outputs
-    Each 5-LUT has an arithemtic mode that converts it to a single-bit adder with both inputs driven by 4-LUTs (both 4-LUTs share all 4 inputs)
-    Carry chain links to vertically adjacent logic blocks
-  - Memory size 32 Kbits, memory aspect ratios vary from a data width of 1 to data width of 64.  
-    Height = 6, found on every (8n+2)th column
-  - Multiplier modes: one 36x36, two 18x18, each 18x18 can also operate as two 9x9.  
-    Height = 4, found on every (8n+6)th column
-  - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1
-
-  Details on Modelling:
-
-  The electrical design of the architecture described here is NOT from an 
-  optimized, SPICED architecture.  Instead, we attempt to create a reasonable 
-  architecture file by using an existing commercial FPGA to approximate the area, 
-  delay, and power of the underlying components. This is combined with a reasonable 40 nm 
-  model of wiring and circuit design for low-level routing components, where available.
-  The resulting architecture has delays that roughly match a commercial 40 nm FPGA, but also 
-  has wiring electrical parameters that allow the wire lengths and switch patterns to be 
-  modified and you will still get reasonable delay results for the new architecture.
-  The following describes, in detail, how we obtained the various electrical values for this 
-  architecture.
-
-  Rmin for nmos and pmos, routing buffer sizes, and I/O pad delays are from the ifar 
-  architecture created by Ian Kuon: K06 N10 45nm fc 0.15 area-delay optimized architecture. 
-  (n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml)      
-  This routing architecture was optimized for 45 nm, and we have scaled it linearly to 40 nm to 
-  match the overall target (a 40 nm FPGA).
-
-  We obtain delay numbers by measuring delays of routing, soft logic blocks, 
-  memories, and multipliers from test circuits on a Stratix IV GX device 
-  (EP4SGX230DF29C2X, i.e. fastest speed grade). For routing, we took the average delay of H4 and V4 
-  wires.  Rmetal and Cmetal values for the routing wires were obtained from work done by Charles 
-  Chiasson. We use a 96 nm half-pitch (corresponding to mid-level metal stack 40 nm routing) and 
-  take the R and C data from the ITRS roadmap.  
-
-  For the general purpose logic block, we assume that the area and delays of the Stratix IV 
-  crossbar is close enough to the crossbar modelled here.  
-  Stratix IV uses 52 inputs and 20 feedback lines, but only a half-populated crossbar, leading to 
-  36:1 multiplexers.  We match these parameters in this architecture.
-
-  For LUTs, we include LUT 
-  delays measured from Stratix IV which is dependant on the input used (ie. some 
-  LUT inputs are faster than others).  The CAD tools at the time of VTR 7 does 
-  not consider differences in LUT input delays.
-
-  Adder delays obtained as approximate values from a Stratix IV EP4SE230F29C3 device.  
-  Delay obtained by compiling a 256 bit adder (registered inputs and outputs, 
-  all pins except clock virtual) then measuring the delays in chip-planner, 
-  sumout delay = 0.271ns to 0.348 ns, intra-block carry delay = 0.011 ns, 
-  inter-block carry delay = 0.327 ns.  Given this data, I will approximate 
-  sumout 0.3 ns, intra-block carry-delay = 0.01 ns, and 
-  inter-block carry-delay = 0.16 ns (since Altera inter-block carry delay has 
-  overhead that we don't have, I'll approximate the delay of a simpler chain at 
-  one half what they have.  This is very rough, anything from 0.01ns to 0.327ns 
-  can be justified).
-
-  Logic block area numbers obtained by scaling overall tile area of a 65nm 
-  Stratix III device, (as given in Wong, Betz and Rose, FPGA 2011) to 40 nm, then subtracting out 
-  routing area at a channel width of 300. We use a channel width of 300 because it can route 
-  all the VTR 6.0 benchmark circuits with an approximately 20% safety margin, and is also close to the
-  total channel width of Stratix IV. Hence this channel width is close to the commercial practice of
-  choosing a width that provides high routability. The architecture can be routed at different channel
-  widths, but we estimate the tile size and hence the physical length of routing wires assuming
-  a channel width of 300.
-
-  Sanity checks employed:
-    1.  We confirmed the routing buffer delay is ~1/3rd of total routing delay at L = 4. This matches 
-        common electrical design.
-
-
-  Authors: Jason Luu, Jeff Goeders, Vaughn Betz
--->
-<architecture>
-  <!-- 
-       ODIN II specific config begins 
-       Describes the types of user-specified netlist blocks (in blif, this corresponds to 
-       ".model [type_of_block]") that this architecture supports.
-
-       Note: Basic LUTs, I/Os, and flip-flops are not included here as there are 
-       already special structures in blif (.names, .input, .output, and .latch) 
-       that describe them.
-  -->
-  <models>
-    <model name="adder">
-      <input_ports>
-        <port name="a" combinational_sink_ports="sumout cout"/>
-        <port name="b" combinational_sink_ports="sumout cout"/>
-        <port name="cin" combinational_sink_ports="sumout cout"/>
-      </input_ports>
-      <output_ports>
-        <port name="cout"/>
-        <port name="sumout"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="io">
-      <input_ports>
-        <port name="outpad"/>
-      </input_ports>
-      <output_ports>
-        <port name="inpad"/>
-      </output_ports>
-    </model>
-    <!-- A virtual model for I/O to be used in the physical mode of io block -->
-    <model name="frac_lut6">
-      <input_ports>
-        <port name="in"/>
-      </input_ports>
-      <output_ports>
-        <port name="lut4_out"/>
-        <port name="lut5_out"/>
-        <port name="lut6_out"/>
-      </output_ports>
-    </model>
-    <model name="dual_port_ram">
-      <input_ports>
-        <!-- write address lines -->
-        <port name="waddr" clock="clk"/>
-        <!-- read address lines -->
-        <port name="raddr" clock="clk"/>
-        <!-- data lines can be broken down into smaller bit widths minimum size 1 -->
-        <port name="d_in" clock="clk"/>
-        <!-- write enable -->
-        <port name="wen" clock="clk"/>
-        <!-- read enable -->
-        <port name="ren" clock="clk"/>
-        <!-- memories are often clocked -->
-        <port name="clk" is_clock="1"/>
-      </input_ports>
-      <output_ports>
-        <!-- output can be broken down into smaller bit widths minimum size 1 -->
-        <port name="d_out" clock="clk"/>
-      </output_ports>
-    </model>
-  </models>
-  <tiles>
-    <tile name="io" capacity="8" area="0">
-      <equivalent_sites>
-        <site pb_type="io"/>
-      </equivalent_sites>
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="custom">
-        <loc side="left">io.outpad io.inpad</loc>
-        <loc side="top">io.outpad io.inpad</loc>
-        <loc side="right">io.outpad io.inpad</loc>
-        <loc side="bottom">io.outpad io.inpad</loc>
-      </pinlocations>
-    </tile>
-    <tile name="clb" area="53894">
-      <equivalent_sites>
-        <site pb_type="clb"/>
-      </equivalent_sites>
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10">
-        <fc_override port_name="cin" fc_type="frac" fc_val="0"/>
-        <fc_override port_name="cout" fc_type="frac" fc_val="0"/>
-      </fc>
-      <!--  Highly recommand to customize pin location when direct connection is used!!! -->
-      <!--pinlocations pattern="spread"/-->
-      <pinlocations pattern="custom">
-        <loc side="left">clb.clk</loc>
-        <loc side="top">clb.cin</loc>
-        <loc side="right">clb.O[9:0] clb.I[19:0]</loc>
-        <loc side="bottom">clb.cout clb.O[19:10] clb.I[39:20]</loc>
-      </pinlocations>
-    </tile>
-    <tile name="memory" height="2" area="548000">
-      <equivalent_sites>
-        <site pb_type="memory"/>
-      </equivalent_sites>
-      <input name="waddr" num_pins="10"/>
-      <input name="raddr" num_pins="10"/>
-      <input name="d_in" num_pins="32"/>
-      <input name="wen" num_pins="1"/>
-      <input name="ren" num_pins="1"/>
-      <output name="d_out" num_pins="32"/>
-      <clock name="clk" num_pins="1"/>
-      <fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
-      <pinlocations pattern="spread"/>
-    </tile>
-  </tiles>
-  <!-- ODIN II specific config ends -->
-  <!-- Physical descriptions begin -->
-  <layout tileable="true" through_channel="true">
-    <!--auto_layout aspect_ratio="1.0"-->
-    <fixed_layout name="4x4" width="5" height="4">
-      <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
-      <perimeter type="io" priority="100"/>
-      <corners type="EMPTY" priority="101"/>
-      <!--Fill with 'clb'-->
-      <fill type="clb" priority="10"/>
-      <!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
-      <col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
-      <col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
-    </fixed_layout>
-    <!-- /auto_layout -->
-  </layout>
-  <device>
-    <!-- VB & JL: Using Ian Kuon's transistor sizing and drive strength data for routing, at 40 nm. Ian used BPTM 
-			     models. We are modifying the delay values however, to include metal C and R, which allows more architecture
-			     experimentation. We are also modifying the relative resistance of PMOS to be 1.8x that of NMOS
-			     (vs. Ian's 3x) as 1.8x lines up with Jeff G's data from a 45 nm process (and is more typical of 
-			     45 nm in general). I'm upping the Rmin_nmos from Ian's just over 6k to nearly 9k, and dropping 
-			     RminW_pmos from 18k to 16k to hit this 1.8x ratio, while keeping the delays of buffers approximately
-			     lined up with Stratix IV. 
-			     We are using Jeff G.'s capacitance data for 45 nm (in tech/ptm_45nm).
-			     Jeff's tables list C in for transistors with widths in multiples of the minimum feature size (45 nm).
-			     The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply drive strength sizes in this file
-	                     by 2.5x when looking up in Jeff's tables.
-			     The delay values are lined up with Stratix IV, which has an architecture similar to this
-			     proposed FPGA, and which is also 40 nm 
-			     C_ipin_cblock: input capacitance of a track buffer, which VPR assumes is a single-stage
-			     4x minimum drive strength buffer. -->
-    <sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
-    <!-- The grid_logic_tile_area below will be used for all blocks that do not explicitly set their own (non-routing)
-     	  area; set to 0 since we explicitly set the area of all blocks currently in this architecture file.
-	    -->
-    <area grid_logic_tile_area="0"/>
-    <chan_width_distr>
-      <x distr="uniform" peak="1.000000"/>
-      <y distr="uniform" peak="1.000000"/>
-    </chan_width_distr>
-    <switch_block type="wilton" fs="3"/>
-    <connection_block input_switch_name="ipin_cblock"/>
-  </device>
-  <switchlist>
-    <!-- VB: the mux_trans_size and buf_size data below is in minimum width transistor *areas*, assuming the purple
-           book area formula. This means the mux transistors are about 5x minimum drive strength.
-           We assume the first stage of the buffer is 3x min drive strength to be reasonable given the large 
-           mux transistors, and this gives a reasonable stage ratio of a bit over 5x to the second stage. We assume
-           the n and p transistors in the first stage are equal-sized to lower the buffer trip point, since it's fed
-           by a pass transistor mux. We can then reverse engineer the buffer second stage to hit the specified 
-           buf_size (really buffer area) - 16.2x minimum drive nmos and 1.8*16.2 = 29.2x minimum drive.
-           I then took the data from Jeff G.'s PTM modeling of 45 nm to get the Cin (gate of first stage) and Cout 
-           (diff of second stage) listed below.  Jeff's models are in tech/ptm_45nm, and are in min feature multiples.
-           The minimum contactable transistor is 2.5 * 45 nm, so I need to multiply the drive strength sizes above by 
-           2.5x when looking up in Jeff's tables.
-           Finally, we choose a switch delay (58 ps) that leads to length 4 wires having a delay equal to that of SIV of 126 ps.
-           This also leads to the switch being 46% of the total wire delay, which is reasonable. -->
-    <switch type="mux" name="0" R="551" Cin=".77e-15" Cout="4e-15" Tdel="58e-12" mux_trans_size="2.630740" buf_size="27.645901"/>
-    <!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
-    <switch type="mux" name="ipin_cblock" R="2231.5" Cout="0." Cin="1.47e-15" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
-  </switchlist>
-  <segmentlist>
-    <!--- VB & JL: using ITRS metal stack data, 96 nm half pitch wires, which are intermediate metal width/space.  
-             With the 96 nm half pitch, such wires would take 60 um of height, vs. a 90 nm high (approximated as square) Stratix IV tile so this seems
-             reasonable. Using a tile length of 90 nm, corresponding to the length of a Stratix IV tile if it were square. -->
-    <!-- GIVE a specific name for the segment! OpenFPGA appreciate that! -->
-    <segment name="L4" freq="1.000000" length="4" type="unidir" Rmetal="101" Cmetal="22.5e-15">
-      <mux name="0"/>
-      <sb type="pattern">1 1 1 1 1</sb>
-      <cb type="pattern">1 1 1 1</cb>
-    </segment>
-  </segmentlist>
-  <directlist>
-    <direct name="adder_carry" from_pin="clb.cout" to_pin="clb.cin" x_offset="0" y_offset="-1" z_offset="0"/>
-  </directlist>
-  <complexblocklist>
-    <!-- Define I/O pads begin -->
-    <!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
-    <!-- Not sure of the area of an I/O (varies widely), and it's not relevant to the design of the FPGA core, so we're setting it to 0. -->
-    <pb_type name="io">
-      <input name="outpad" num_pins="1"/>
-      <output name="inpad" num_pins="1"/>
-
-      <!-- Do NOT add clock pins to I/O here!!! VPR does not build clock network in the way that OpenFPGA can support
-           If you need to register the I/O, define clocks in the circuit models
-           These clocks can be handled in back-end
-       -->
-      <!-- A mode denotes the physical implementation of an I/O 
-           This mode will be not packable but is mainly used for fabric verilog generation   
-        -->
-      <mode name="physical" disabled_in_pack="true">
-        <pb_type name="iopad" blif_model=".subckt io" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="iopad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="iopad.outpad"/>
-          </direct>
-          <direct name="inpad" input="iopad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="iopad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-
-      <!-- IOs can operate as either inputs or outputs.
-	     Delays below come from Ian Kuon. They are small, so they should be interpreted as
-	     the delays to and from registers in the I/O (and generally I/Os are registered 
-	     today and that is when you timing analyze them.
-	     -->
-      <mode name="inpad">
-        <pb_type name="inpad" blif_model=".input" num_pb="1">
-          <output name="inpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="inpad" input="inpad.inpad" output="io.inpad">
-            <delay_constant max="4.243e-11" in_port="inpad.inpad" out_port="io.inpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <mode name="outpad">
-        <pb_type name="outpad" blif_model=".output" num_pb="1">
-          <input name="outpad" num_pins="1"/>
-        </pb_type>
-        <interconnect>
-          <direct name="outpad" input="io.outpad" output="outpad.outpad">
-            <delay_constant max="1.394e-11" in_port="io.outpad" out_port="outpad.outpad"/>
-          </direct>
-        </interconnect>
-      </mode>
-      <!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
-      <!-- IOs go on the periphery of the FPGA, for consistency, 
-          make it physically equivalent on all sides so that only one definition of I/Os is needed.
-          If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
-        -->
-      <!-- Place I/Os on the sides of the FPGA -->
-      <power method="ignore"/>
-    </pb_type>
-    <!-- Define I/O pads ends -->
-    <!-- Define general purpose logic block (CLB) begin -->
-    <!--- Area calculation: Total Stratix IV tile area is about 8100 um^2, and a minimum width transistor 
-	   area is 60 L^2 yields a tile area of 84375 MWTAs.
-	   Routing at W=300 is 30481 MWTAs, leaving us with a total of 53000 MWTAs for logic block area 
-	   This means that only 37% of our area is in the general routing, and 63% is inside the logic
-	   block. Note that the crossbar / local interconnect is considered part of the logic block
-	   area in this analysis. That is a lower proportion of of routing area than most academics
-	   assume, but note that the total routing area really includes the crossbar, which would push
-	   routing area up significantly, we estimate into the ~70% range. 
-	   -->
-    <pb_type name="clb">
-      <input name="I" num_pins="40" equivalent="full"/>
-      <input name="cin" num_pins="1"/>
-      <output name="O" num_pins="20" equivalent="none"/>
-      <output name="cout" num_pins="1"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Describe fracturable logic element.  
-             Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs. 
-             The outputs of the fracturable logic element can be optionally registered
-        -->
-      <pb_type name="fle" num_pb="10">
-        <input name="in" num_pins="6"/>
-        <input name="cin" num_pins="1"/>
-        <output name="out" num_pins="2"/>
-        <output name="cout" num_pins="1"/>
-        <clock name="clk" num_pins="1"/>
-        <!-- Physical mode definition begin (physical implementation of the fle) -->
-        <mode name="physical" disabled_in_pack="true">
-          <pb_type name="fabric" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="2"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="frac_logic" num_pb="1">
-              <input name="in" num_pins="6"/>
-              <output name="lut4_out" num_pins="4"/>
-              <output name="out" num_pins="2"/>
-              <!-- Define LUT -->
-              <pb_type name="frac_lut6" blif_model=".subckt frac_lut6" num_pb="1">
-                <input name="in" num_pins="6"/>
-                <output name="lut4_out" num_pins="4"/>
-                <output name="lut5_out" num_pins="2"/>
-                <output name="lut6_out" num_pins="1"/>
-              </pb_type>
-              <interconnect>
-                <direct name="direct1" input="frac_logic.in" output="frac_lut6.in"/>
-                <direct name="direct2" input="frac_lut6.lut4_out" output="frac_logic.lut4_out"/>
-                <direct name="direct3" input="frac_lut6.lut5_out[1]" output="frac_logic.out[1]"/>
-                <!-- Xifan Tang: I use out[0] because the output of lut6 in lut6 mode is wired to the out[0] -->
-                <mux name="mux1" input="frac_lut6.lut6_out frac_lut6.lut5_out[0]" output="frac_logic.out[0]"/>
-              </interconnect>
-            </pb_type>
-            <!-- Define flip-flop -->
-            <pb_type name="ff" blif_model=".latch" num_pb="2" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>         
-            <!-- Define adders -->
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="2">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="fabric.in" output="frac_logic.in"/>
-              <direct name="direct2" input="frac_logic.out[1:0]" output="ff[1:0].D"/>
-              <direct name="direct3" input="fabric.cin" output="adder[0:0].cin"/>
-              <direct name="direct4" input="adder[0:0].cout" output="adder[1:1].cin"/>
-              <direct name="direct5" input="adder[1:1].cout" output="fabric.cout"/>
-              <direct name="direct6" input="frac_logic.lut4_out[0:0]" output="adder[0:0].a"/>
-              <direct name="direct7" input="frac_logic.lut4_out[1:1]" output="adder[0:0].b"/>
-              <direct name="direct8" input="frac_logic.lut4_out[2:2]" output="adder[1:1].a"/>
-              <direct name="direct9" input="frac_logic.lut4_out[3:3]" output="adder[1:1].b"/>
-              <complete name="direct10" input="fabric.clk" output="ff[1:0].clk"/>
-              <mux name="mux1" input="adder[0].sumout ff[0].Q frac_logic.out[0]" output="fabric.out[0]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[0]" out_port="fabric.out[0]"/>
-                <delay_constant max="45e-12" in_port="ff[0].Q" out_port="fabric.out[0]"/>
-              </mux>
-              <mux name="mux2" input="adder[1].sumout ff[1].Q frac_logic.out[1]" output="fabric.out[1]">
-                <!-- LUT to output is faster than FF to output on a Stratix IV -->
-                <delay_constant max="25e-12" in_port="frac_logic.out[1]" out_port="fabric.out[1]"/>
-                <delay_constant max="45e-12" in_port="ff[1].Q" out_port="fabric.out[1]"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in" output="fabric.in"/>
-            <direct name="direct2" input="fle.cin" output="fabric.cin"/>
-            <direct name="direct3" input="fabric.out" output="fle.out"/>
-            <direct name="direct4" input="fabric.cout" output="fle.cout"/>
-            <direct name="direct5" input="fle.clk" output="fabric.clk"/>
-          </interconnect>
-        </mode>
-        <!-- Physical mode definition end (physical implementation of the fle) -->
-        <!-- BEGIN fle mode of dual lut5 -->
-        <mode name="n2_lut5">
-          <pb_type name="ble5" num_pb="2">
-            <input name="in" num_pins="5"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Regular LUT mode -->
-            <pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="5" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                  we instead take the average of these numbers to get more stable results
-                82e-12
-                173e-12
-                261e-12
-                263e-12
-                398e-12
-                -->
-              <delay_matrix type="max" in_port="lut5.in" out_port="lut5.out">
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-                235e-12
-              </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble5.in" output="lut5.in"/>
-              <direct name="direct2" input="lut5.out" output="ff.D">
-                <pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble5.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut5.out" output="ble5.out">
-                <delay_constant max="25e-12" in_port="lut5.out" out_port="ble5.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble5.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[4:0]" output="ble5[0:0].in"/>
-            <direct name="direct2" input="fle.in[4:0]" output="ble5[1:1].in"/>
-            <complete name="direct3" input="fle.clk" output="ble5.clk"/>
-            <direct name="direct4" input="ble5.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- END fle mode of dual lut5 -->
-        <!-- BEGIN arithmetic mode of dual lut4 + adders -->
-        <mode name="arithmetic">
-          <pb_type name="arithmetic" num_pb="2">
-            <input name="in" num_pins="4"/>
-            <input name="cin" num_pins="1"/>
-            <output name="out" num_pins="1"/>
-            <output name="cout" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <!-- Special dual-LUT mode that drives adder only -->
-            <pb_type name="lut4" blif_model=".names" num_pb="2" class="lut">
-              <input name="in" num_pins="4" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  -->
-              <delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
-                  195e-12
-                  195e-12
-                  195e-12
-                  195e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="adder" blif_model=".subckt adder" num_pb="1">
-              <input name="a" num_pins="1"/>
-              <input name="b" num_pins="1"/>
-              <input name="cin" num_pins="1"/>
-              <output name="cout" num_pins="1"/>
-              <output name="sumout" num_pins="1"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.cin" out_port="adder.sumout"/>
-              <delay_constant max="0.3e-9" in_port="adder.a" out_port="adder.cout"/>
-              <delay_constant max="0.3e-9" in_port="adder.b" out_port="adder.cout"/>
-              <delay_constant max="0.01e-9" in_port="adder.cin" out_port="adder.cout"/>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="clock" input="arithmetic.clk" output="ff.clk"/>
-              <direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
-              <direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
-              <direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
-                </direct>
-              <direct name="lut_to_add2" input="lut4[1:1].out" output="adder.b">
-                </direct>
-              <direct name="add_to_ff" input="adder.sumout" output="ff.D">
-                <pack_pattern name="chain" in_port="adder.sumout" out_port="ff.D"/>
-              </direct>
-              <direct name="carry_in" input="arithmetic.cin" output="adder.cin">
-                <pack_pattern name="chain" in_port="arithmetic.cin" out_port="adder.cin"/>
-              </direct>
-              <direct name="carry_out" input="adder.cout" output="arithmetic.cout">
-                <pack_pattern name="chain" in_port="adder.cout" out_port="arithmetic.cout"/>
-              </direct>
-              <mux name="sumout" input="ff.Q adder.sumout" output="arithmetic.out">
-                <delay_constant max="25e-12" in_port="adder.sumout" out_port="arithmetic.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="arithmetic.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[3:0]" output="arithmetic[0:0].in"/>
-            <direct name="direct2" input="fle.in[3:0]" output="arithmetic[1:1].in"/>
-            <direct name="carry_in" input="fle.cin" output="arithmetic[0:0].cin">
-              <pack_pattern name="chain" in_port="fle.cin" out_port="arithmetic[0:0].cin"/>
-            </direct>
-            <direct name="carry_inter" input="arithmetic[0:0].cout" output="arithmetic[1:1].cin">
-              <pack_pattern name="chain" in_port="arithmetic[0:0].cout" out_port="arithmetic[1:1].cin"/>
-            </direct>
-            <direct name="carry_out" input="arithmetic[1:1].cout" output="fle.cout">
-              <pack_pattern name="chain" in_port="arithmetic.cout" out_port="fle.cout"/>
-            </direct>
-            <complete name="direct3" input="fle.clk" output="arithmetic.clk"/>
-            <direct name="direct4" input="arithmetic.out" output="fle.out"/>
-          </interconnect>
-        </mode>
-        <!-- n2_lut5 -->
-        <mode name="n1_lut6">
-          <pb_type name="ble6" num_pb="1">
-            <input name="in" num_pins="6"/>
-            <output name="out" num_pins="1"/>
-            <clock name="clk" num_pins="1"/>
-            <pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
-              <input name="in" num_pins="6" port_class="lut_in"/>
-              <output name="out" num_pins="1" port_class="lut_out"/>
-              <!-- LUT timing using delay matrix -->
-              <!-- These are the physical delay inputs on a Stratix IV LUT but because VPR cannot do LUT rebalancing,
-                       we instead take the average of these numbers to get more stable results
-                  82e-12
-                  173e-12
-                  261e-12
-                  263e-12
-                  398e-12
-                  397e-12
-                  -->
-              <delay_matrix type="max" in_port="lut6.in" out_port="lut6.out">
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                  261e-12
-                </delay_matrix>
-            </pb_type>
-            <pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
-              <input name="D" num_pins="1" port_class="D"/>
-              <output name="Q" num_pins="1" port_class="Q"/>
-              <clock name="clk" num_pins="1" port_class="clock"/>
-              <T_setup value="66e-12" port="ff.D" clock="clk"/>
-              <T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
-            </pb_type>
-            <interconnect>
-              <direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
-              <direct name="direct2" input="lut6.out" output="ff.D">
-                <pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
-              </direct>
-              <direct name="direct3" input="ble6.clk" output="ff.clk"/>
-              <mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
-                <delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out"/>
-                <delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out"/>
-              </mux>
-            </interconnect>
-          </pb_type>
-          <interconnect>
-            <direct name="direct1" input="fle.in[5:0]" output="ble6.in"/>
-            <direct name="direct2" input="ble6.out" output="fle.out[0:0]"/>
-            <direct name="direct3" input="fle.clk" output="ble6.clk"/>
-          </interconnect>
-        </mode>
-        <!-- n1_lut6 -->
-      </pb_type>
-      <interconnect>
-        <!-- We use a 50% depop crossbar built using small full xbars to get sets of logically equivalent pins at inputs of CLB 
-           The delays below come from Stratix IV. the delay through a connection block
-           input mux + the crossbar in Stratix IV is 167 ps. We already have a 72 ps 
-           delay on the connection block input mux (modeled by Ian Kuon), so the remaining
-           delay within the crossbar is 95 ps. 
-           The delays of cluster feedbacks in Stratix IV is 100 ps, when driven by a LUT.
-           Since all our outputs LUT outputs go to a BLE output, and have a delay of 
-           25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback
-           to get the part that should be marked on the crossbar.	 -->
-        <complete name="crossbar" input="clb.I fle[9:0].out" output="fle[9:0].in">
-          <delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in"/>
-          <delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in"/>
-        </complete>
-
-        <complete name="clks" input="clb.clk" output="fle[9:0].clk">
-        </complete>
-        <!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.  
-                 By grouping to output pins in this fashion, if a logic block is completely filled by 6-LUTs, 
-                 then the outputs those 6-LUTs take get evenly distributed across all four sides of the CLB instead of clumped on two sides (which is what happens with a more
-                 naive specification).
-          -->
-        <direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
-        <direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
-        <!-- Carry chain links -->
-        <direct name="carry_in" input="clb.cin" output="fle[0:0].cin">
-          <!-- Put all inter-block carry chain delay on this one edge -->
-          <delay_constant max="0.16e-9" in_port="clb.cin" out_port="fle[0:0].cin"/>
-          <pack_pattern name="chain" in_port="clb.cin" out_port="fle[0:0].cin"/>
-        </direct>
-        <direct name="carry_out" input="fle[9:9].cout" output="clb.cout">
-          <pack_pattern name="chain" in_port="fle[9:9].cout" out_port="clb.cout"/>
-        </direct>
-        <direct name="carry_link" input="fle[8:0].cout" output="fle[9:1].cin">
-          <pack_pattern name="chain" in_port="fle[8:0].cout" out_port="fle[9:1].cin"/>
-        </direct>
-      </interconnect>
-    </pb_type>
-    <!-- Define general purpose logic block (CLB) ends -->
-    <!-- Define single-mode dual-port memory begin -->
-    <pb_type name="memory">
-      <input name="waddr" num_pins="10"/>
-      <input name="raddr" num_pins="10"/>
-      <input name="d_in" num_pins="32"/>
-      <input name="wen" num_pins="1"/>
-      <input name="ren" num_pins="1"/>
-      <output name="d_out" num_pins="32"/>
-      <clock name="clk" num_pins="1"/>
-      <!-- Specify the 512x32=16Kbit memory block
-           Note: the delay numbers are extracted from VPR flagship XML without modification
-                 Should align to the process technology we using to create the 16K dual-port RAM
-        -->
-      <mode name="mem_512x32_dp">
-        <pb_type name="mem_512x32_dp" blif_model=".subckt dual_port_ram" class="memory" num_pb="1">
-          <input name="waddr" num_pins="10" port_class="address"/>
-          <input name="raddr" num_pins="10" port_class="address"/>
-          <input name="d_in" num_pins="32" port_class="data_in"/>
-          <input name="wen" num_pins="1" port_class="write_en"/>
-          <input name="ren" num_pins="1" port_class="write_en"/>
-          <output name="d_out" num_pins="32" port_class="data_out"/>
-          <clock name="clk" num_pins="1" port_class="clock"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.waddr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.raddr" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.d_in" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.wen" clock="clk"/>
-          <T_setup value="509e-12" port="mem_512x32_dp.ren" clock="clk"/>
-          <T_clock_to_Q max="1.234e-9" port="mem_512x32_dp.d_out" clock="clk"/>
-          <power method="pin-toggle">
-            <port name="clk" energy_per_toggle="17.9e-12"/>
-            <static_power power_per_instance="0.0"/>
-          </power>
-        </pb_type>
-        <interconnect>
-          <direct name="waddress" input="memory.waddr" output="mem_512x32_dp.waddr">
-            <delay_constant max="132e-12" in_port="memory.waddr" out_port="mem_512x32_dp.waddr"/>
-          </direct>
-          <direct name="raddress" input="memory.raddr" output="mem_512x32_dp.raddr">
-            <delay_constant max="132e-12" in_port="memory.raddr" out_port="mem_512x32_dp.raddr"/>
-          </direct>
-          <direct name="data_input" input="memory.d_in" output="mem_512x32_dp.d_in">
-            <delay_constant max="132e-12" in_port="memory.d_in" out_port="mem_512x32_dp.d_in"/>
-          </direct>
-          <direct name="writeen" input="memory.wen" output="mem_512x32_dp.wen">
-            <delay_constant max="132e-12" in_port="memory.wen" out_port="mem_512x32_dp.wen"/>
-          </direct>
-          <direct name="readen" input="memory.ren" output="mem_512x32_dp.ren">
-            <delay_constant max="132e-12" in_port="memory.ren" out_port="mem_512x32_dp.ren"/>
-          </direct>
-          <direct name="dataout" input="mem_512x32_dp.d_out" output="memory.d_out">
-            <delay_constant max="40e-12" in_port="mem_512x32_dp.d_out" out_port="memory.d_out"/>
-          </direct>
-          <direct name="clk" input="memory.clk" output="mem_512x32_dp.clk">
-          </direct>
-        </interconnect>
-      </mode>
-    </pb_type>
-    <!-- Define single-mode dual-port memory end -->
-  </complexblocklist>
-</architecture>

openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga

@@ -1,17 +1,16 @@
 # Run VPR for the 'and' design
-vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml
+#--write_rr_graph example_rr_graph.xml
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH}
 
 # Read OpenFPGA architecture definition
-read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml
+read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
 
-# Write out the architecture XML as a proof
-#write_openfpga_arch -f ./arch_echo.xml
+# Read OpenFPGA simulation settings
+read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE}
 
 # Annotate the OpenFPGA architecture to VPR data base
-link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose
-
-# Write GSB to XML for debugging
-write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml
+# to debug use --verbose options
+link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges
 
 # Check and correct any naming conflicts in the BLIF netlist
 check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
@@ -20,12 +19,16 @@ check_netlist_naming_conflict --fix --report ./netlist_renaming.xml
 pb_pin_fixup --verbose
 
 # Apply fix-up to Look-Up Table truth tables based on packing results
-lut_truth_table_fixup #--verbose
+lut_truth_table_fixup
 
 # Build the module graph
 #  - Enabled compression on routing architecture modules
 #  - Enable pin duplication on grid modules
-build_fabric --compress_routing --duplicate_grid_pin --verbose
+build_fabric --compress_routing #--verbose
+
+# Write the fabric hierarchy of module graph to a file
+# This is used by hierarchical PnR flows
+write_fabric_hierarchy --file ./fabric_hierarchy.txt
 
 # Repack the netlist to physical pbs
 # This must be done before bitstream generator and testbench generation
@@ -34,14 +37,17 @@ repack #--verbose
 
 # Build the bitstream
 #  - Output the fabric-independent bitstream to a file
-build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml
+build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml
 
 # Build fabric-dependent bitstream
 build_fabric_bitstream --verbose
 
+# Write fabric-dependent bitstream
+write_fabric_bitstream --file fabric_bitstream.xml --format xml
+
 # Write the Verilog netlist for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
-write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
+write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose
 
 # Write the Verilog testbench for FPGA fabric
 #  - We suggest the use of same output directory as fabric Verilog netlists
@@ -49,14 +55,20 @@ write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port
 #  - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA
 #  - Enable pre-configured top-level testbench which is a fast verification skipping programming phase
 #  - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts
-write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini
+write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping
 
 # Write the SDC files for PnR backend
 #  - Turn on every options here
-write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC 
+write_pnr_sdc --file ./SDC
+
+# Write SDC to disable timing for configure ports
+write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc
 
 # Write the SDC to run timing analysis for a mapped FPGA fabric
-write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis
+write_analysis_sdc --file ./SDC_analysis
 
 # Finish and exit OpenFPGA
 exit
+
+# Note :
+# To run verification at the end of the flow maintain source in ./SRC directory

openfpga_flow/VerilogNetlists/adder.v

@@ -1,19 +1,20 @@
-//------ Module: sram6T_blwl -----//
-//------ Verilog file: sram.v -----//
-//------ Author: Xifan TANG -----//
-module adder(
-input [0:0] a, // Input a
-input [0:0] b, // Input b
-input [0:0] cin, // Input cin
-output [0:0] cout, // Output carry
-output [0:0] sumout // Output sum
-);
-//wire[1:0] int_calc;
+//-----------------------------------------------------
+// Design Name : Multi-bit Full Adder
+// File Name   : adder.v
+// Coder       : Xifan TANG
+//-----------------------------------------------------
 
-//assign int_calc = a + b + cin;
-//assign cout = int_calc[1];
-//assign sumout = int_calc[0];
-  assign sumout = a ^ b ^ cin;
-  assign cout = (a & b) | (a & cin) | (b & cin); 
+//-----------------------------------------------------
+// Function    : A 1-bit full adder
+//-----------------------------------------------------
+module ADDF(
+  input [0:0] A, // Input a
+  input [0:0] B, // Input b
+  input [0:0] CI, // Input cin
+  output [0:0] CO, // Output carry
+  output [0:0] SUM // Output sum
+);
+  assign SUM = A ^ B ^ CI;
+  assign CO = (A & B) | (A & CI) | (B & CI); 
 endmodule
 

openfpga_flow/VerilogNetlists/aib.v

@@ -5,12 +5,12 @@
 // Coder       : Xifan Tang
 //-----------------------------------------------------
 
-module aib (
-	input tx_clk,
-	input rx_clk,
-	inout[0:79] pad,
-	input[0:79] tx_data,
-	output[0:79] rx_data);
+module AIB (
+	input TX_CLK,
+	input RX_CLK,
+	inout[0:79] PAD,
+	input[0:79] TX_DATA,
+	output[0:79] RX_DATA);
 
 // May add the logic function of a real AIB
 // Refer to the offical AIB github

openfpga_flow/VerilogNetlists/config_latch.v

@@ -1,38 +0,0 @@
-//-----------------------------------------------------
-// Design Name : config_latch
-// File Name   : config_latch.v
-// Function    : A Configurable Latch where data storage
-//               can be updated at rising clock edge 
-//               when wl is enabled
-// Coder       : Xifan TANG
-//-----------------------------------------------------
-module config_latch (
-  input reset, // Reset input
-  input clk, // Clock Input
-  input wl, // Data Enable
-  input bl, // Data Input
-  output Q, // Q output
-  output Qb // Q output
-);
-//------------Internal Variables--------
-reg q_reg;
-
-//-------------Code Starts Here---------
-always @ ( posedge clk or posedge reset) begin
-  if (reset) begin
-    q_reg <= 1'b0;
-  end else if (1'b1 == wl) begin
-    q_reg <= bl;
-  end
-end
-
-`ifndef ENABLE_FORMAL_VERIFICATION
-// Wire q_reg to Q
-assign Q = q_reg;
-assign Qb = ~q_reg;
-`else
-assign Q = 1'bZ;
-assign Qb = !Q;
-`endif
-
-endmodule

openfpga_flow/VerilogNetlists/dff.v

@@ -0,0 +1,311 @@
+//-----------------------------------------------------
+// Design Name : D-type Flip-flops
+// File Name   : ff.v
+// Coder       : Xifan TANG
+//-----------------------------------------------------
+
+//-----------------------------------------------------
+// Function    : A native D-type flip-flop
+//-----------------------------------------------------
+module DFF (
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q, // Q output
+  output QN // QB output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ (posedge CK) begin 
+  q_reg <= D;
+end
+
+// Wire q_reg to Q
+`ifndef ENABLE_FORMAL_VERIFICATION
+  assign Q = q_reg;
+  assign QN = ~q_reg;
+`else
+  assign Q = 1'bZ;
+  assign QN = !Q;
+`endif
+
+endmodule //End Of Module
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active high reset
+//-----------------------------------------------------
+module DFFR (
+  input RST, // Reset input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q, // Q output
+  output QN // QB output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST)
+if (RST) begin
+  q_reg <= 1'b0;
+end else begin
+  q_reg <= D;
+end
+
+// Wire q_reg to Q
+`ifndef ENABLE_FORMAL_VERIFICATION
+  assign Q = q_reg;
+  assign QN = ~q_reg;
+`else
+  assign Q = 1'bZ;
+  assign QN = !Q;
+`endif
+
+endmodule //End Of Module
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active low reset
+//-----------------------------------------------------
+module DFFRN (
+  input RSTN, // Reset input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q, // Q output
+  output QN // QB output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or negedge RSTN)
+if (~RSTN) begin
+  q_reg <= 1'b0;
+end else begin
+  q_reg <= D;
+end
+
+// Wire q_reg to Q
+`ifndef ENABLE_FORMAL_VERIFICATION
+  assign Q = q_reg;
+  assign QN = ~q_reg;
+`else
+  assign Q = 1'bZ;
+  assign QN = !Q;
+`endif
+
+endmodule //End Of Module
+
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active high set
+//-----------------------------------------------------
+module DFFS (
+  input SET, // Set input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q, // Q output
+  output QN // QB output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge SET)
+if (SET) begin
+  q_reg <= 1'b1;
+end else begin
+  q_reg <= D;
+end
+
+// Wire q_reg to Q
+`ifndef ENABLE_FORMAL_VERIFICATION
+  assign Q = q_reg;
+  assign QN = ~q_reg;
+`else
+  assign Q = 1'bZ;
+  assign QN = !Q;
+`endif
+
+endmodule //End Of Module
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active low set
+//-----------------------------------------------------
+module DFFSN (
+  input SETN, // Set input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q, // Q output
+  output QN // QB output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or negedge SETN)
+if (~SETN) begin
+  q_reg <= 1'b1;
+end else begin
+  q_reg <= D;
+end
+
+// Wire q_reg to Q
+`ifndef ENABLE_FORMAL_VERIFICATION
+  assign Q = q_reg;
+  assign QN = ~q_reg;
+`else
+  assign Q = 1'bZ;
+  assign QN = !Q;
+`endif
+
+endmodule //End Of Module
+
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active high reset
+//               - asynchronous active high set
+//-----------------------------------------------------
+module DFFSR (
+  input SET, // set input
+  input RST, // Reset input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q, // Q output
+  output QN // QB output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST or posedge SET)
+if (RST) begin
+  q_reg <= 1'b0;
+end else if (SET) begin
+  q_reg <= 1'b1;
+end else begin
+  q_reg <= D;
+end
+
+// Wire q_reg to Q
+`ifndef ENABLE_FORMAL_VERIFICATION
+  assign Q = q_reg;
+  assign QN = ~q_reg;
+`else
+  assign Q = 1'bZ;
+  assign QN = !Q;
+`endif
+
+endmodule //End Of Module
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active high reset
+//               - asynchronous active high set
+//-----------------------------------------------------
+module DFFSRQ (
+  input SET, // set input
+  input RST, // Reset input
+  input CK, // Clock Input
+  input D, // Data Input
+  output Q // Q output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST or posedge SET)
+if (RST) begin
+  q_reg <= 1'b0;
+end else if (SET) begin
+  q_reg <= 1'b1;
+end else begin
+  q_reg <= D;
+end
+
+assign Q = q_reg;
+
+endmodule //End Of Module
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active high reset
+//               - asynchronous active high set
+//               - scan-chain input
+//               - a scan-chain enable 
+//-----------------------------------------------------
+module SDFFSR (
+  input SET, // Set input
+  input RST, // Reset input
+  input CK, // Clock Input
+  input SE, // Scan-chain Enable
+  input D, // Data Input
+  input SI, // Scan-chain input
+  output Q, // Q output
+  output QN // Q negative output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST or posedge SET)
+if (RST) begin
+  q_reg <= 1'b0;
+end else if (SET) begin
+  q_reg <= 1'b1;
+end else if (SE) begin
+  q_reg <= SI;
+end else begin
+  q_reg <= D;
+end
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+// Wire q_reg to Q
+  assign Q = q_reg;
+  assign QN = !Q;
+`else
+  assign Q = 1'bZ;
+  assign QN = !Q;
+`endif
+
+endmodule //End Of Module
+
+//-----------------------------------------------------
+// Function    : D-type flip-flop with 
+//               - asynchronous active high reset
+//               - asynchronous active high set
+//               - scan-chain input
+//               - a scan-chain enable 
+//-----------------------------------------------------
+module SDFFSRQ (
+  input SET, // Set input
+  input RST, // Reset input
+  input CK, // Clock Input
+  input SE, // Scan-chain Enable
+  input D, // Data Input
+  input SI, // Scan-chain input
+  output Q // Q output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST or posedge SET)
+if (RST) begin
+  q_reg <= 1'b0;
+end else if (SET) begin
+  q_reg <= 1'b1;
+end else if (SE) begin
+  q_reg <= SI;
+end else begin
+  q_reg <= D;
+end
+
+assign Q = q_reg;
+
+endmodule //End Of Module

openfpga_flow/VerilogNetlists/ff.v

@@ -1,146 +0,0 @@
-//-----------------------------------------------------
-// Design Name : static_dff
-// File Name   : ff.v
-// Function    : D flip-flop with asyn reset and set
-// Coder       : Xifan TANG
-//-----------------------------------------------------
-//------ Include defines: preproc flags -----
-// `include "./SRC/fpga_defines.v"
-module static_dff (
-/* Global ports go first */
-input set,     // set input
-input reset, // Reset input
-input clk, // Clock Input
-/* Local ports follow */
-input D, // Data Input
-output Q // Q output
-);
-//------------Internal Variables--------
-reg q_reg;
-
-//-------------Code Starts Here---------
-always @ ( posedge clk or posedge reset or posedge set)
-if (reset) begin
-  q_reg <= 1'b0;
-end else if (set) begin
-  q_reg <= 1'b1;
-end else begin
-  q_reg <= D;
-end
-
-// Wire q_reg to Q
-assign Q = q_reg;
-
-endmodule //End Of Module static_dff
-
-module scan_chain_ff (
-/* Global ports go first */
-input set,     // set input
-input reset, // Reset input
-input clk, // Clock Input
-input TESTEN, // Clock Input
-/* Local ports follow */
-input D, // Data Input
-input DI, // Scan Chain Data Input
-output Q // Q output
-);
-//------------Internal Variables--------
-reg q_reg;
-
-//-------------Code Starts Here---------
-always @ ( posedge clk or posedge reset or posedge set)
-if (reset) begin
-  q_reg <= 1'b0;
-end else if (set) begin
-  q_reg <= 1'b1;
-end else if (TESTEN) begin
-  q_reg <= DI;
-end else begin
-  q_reg <= D;
-end
-
-// Wire q_reg to Q
-assign Q = q_reg;
-
-endmodule //End Of Module static_dff
-
-
-//-----------------------------------------------------
-// Design Name : scan_chain_dff
-// File Name   : ff.v
-// Function    : D flip-flop with asyn reset and set
-// Coder       : Xifan TANG
-//-----------------------------------------------------
-module sc_dff (
-/* Global ports go first */
-input set,     // set input
-input reset, // Reset input
-input clk, // Clock Input
-/* Local ports follow */
-input D, // Data Input
-output Q, // Q output
-output Qb // Q output
-);
-//------------Internal Variables--------
-reg q_reg;
-
-//-------------Code Starts Here---------
-always @ ( posedge clk or posedge reset or posedge set)
-if (reset) begin
-  q_reg <= 1'b0;
-end else if (set) begin
-  q_reg <= 1'b1;
-end else begin
-  q_reg <= D;
-end
-
-// Wire q_reg to Q
-assign Q = q_reg;
-assign Qb = ~Q;
-
-endmodule //End Of Module static_dff
-
-//-----------------------------------------------------
-// Design Name : scan_chain_dff compact
-// File Name   : ff.v
-// Function    : Scan-chain D flip-flop without reset and set	//Modified to fit Edouards architecture
-// Coder       : Xifan TANG
-//-----------------------------------------------------
-module sc_dff_compact (
-/* Global ports go first */
-input reset, // Reset input
-//input set,     // set input
-input clk, // Clock Input
-/* Local ports follow */
-input D, // Data Input
-output Q, // Q output
-output Qb // Q output
-);
-//------------Internal Variables--------
-reg q_reg;
-
-//-------------Code Starts Here---------
-always @ ( posedge clk or posedge reset /*or posedge set*/)
-if (reset) begin
-  q_reg <= 1'b0;
-//end else if (set) begin
-//  q_reg <= 1'b1;
-end else begin
-  q_reg <= D;
-end
-/*
-// Wire q_reg to Q
-assign Q = q_reg;
-assign Qb = ~Q;
-*/
-
-`ifndef ENABLE_FORMAL_VERIFICATION
-// Wire q_reg to Q
-assign Q = q_reg;
-assign Qb = ~q_reg;
-`else
-assign Q = 1'bZ;
-assign Qb = !Q;
-`endif
-
-endmodule //End Of Module static_dff

openfpga_flow/VerilogNetlists/gpio.v

@@ -0,0 +1,20 @@
+//-----------------------------------------------------
+// Design Name : General Purpose I/Os
+// File Name   : gpio.v
+// Coder       : Xifan TANG
+//-----------------------------------------------------
+
+//-----------------------------------------------------
+// Function    : A minimum general purpose I/O
+//-----------------------------------------------------
+module GPIO (
+  input A, // Data output
+  output Y, // Data input
+  inout PAD, // bi-directional pad
+  input DIR // direction control
+);
+  //----- when direction enabled, the signal is propagated from PAD to data input
+  assign Y = DIR ? PAD : 1'bz;
+  //----- when direction is disabled, the signal is propagated from data out to pad
+  assign PAD = DIR ? 1'bz : A;
+endmodule

openfpga_flow/VerilogNetlists/io.v

@@ -1,16 +0,0 @@
-//------ Module: iopad -----//
-//------ Verilog file: io.v -----//
-//------ Author: Xifan TANG -----//
-module iopad(
-//input zin, // Set output to be Z
-input outpad, // Data output
-output inpad, // Data input
-inout pad, // bi-directional pad
-input en // enable signal to control direction of iopad
-//input direction_inv // enable signal to control direction of iopad
-);
-  //----- when direction enabled, the signal is propagated from pad to din
-  assign inpad = en ? pad : 1'bz;
-  //----- when direction is disabled, the signal is propagated from dout to pad
-  assign pad = en ? 1'bz : outpad;
-endmodule

openfpga_flow/VerilogNetlists/latch.v

@@ -0,0 +1,255 @@
+//-----------------------------------------------------
+// Design Name : config_latch
+// File Name   : config_latch.v
+// Coder       : Xifan TANG
+//-----------------------------------------------------
+
+//-----------------------------------------------------
+// Function    : A Configurable Latch with
+//               - an active-high write enable signal
+//-----------------------------------------------------
+module LATCH (
+  input WE, // Write enable
+  input D, // Data input
+  output Q, // Q output
+  output QN // Q negative output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ (WE or D) begin
+  if (1'b1 == WE) begin
+    q_reg <= D;
+  end
+end
+
+// Wire q_reg to Q
+`ifndef ENABLE_FORMAL_VERIFICATION
+  assign Q = q_reg;
+  assign QN = ~q_reg;
+`else
+  assign Q = 1'bZ;
+  assign QN = !Q;
+`endif
+
+endmodule
+
+//-----------------------------------------------------
+// Function    : A Configurable Latch with
+//               - an active-high write enable signal
+//               - an active-high reset signal
+//-----------------------------------------------------
+module LATCHR (
+  input RST, // Reset signal
+  input WE, // Write enable
+  input D, // Data input
+  output Q, // Q output
+  output QN // Q negative output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ (RST or WE or D) begin
+  if (RST) begin
+    q_reg <= 1'b0;
+  end else if (1'b1 == WE) begin
+    q_reg <= D;
+  end
+end
+
+// Wire q_reg to Q
+`ifndef ENABLE_FORMAL_VERIFICATION
+  assign Q = q_reg;
+  assign QN = ~q_reg;
+`else
+  assign Q = 1'bZ;
+  assign QN = !Q;
+`endif
+
+endmodule
+
+//-----------------------------------------------------
+// Function    : A Configurable Latch with
+//               - an active-high write enable signal
+//               - an active-low reset signal
+//-----------------------------------------------------
+module LATCHRN (
+  input RSTN, // Reset signal
+  input WE, // Write enable
+  input D, // Data input
+  output Q, // Q output
+  output QN // Q negative output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ (RSTN or WE or D) begin
+  if (~RSTN) begin
+    q_reg <= 1'b0;
+  end else if (1'b1 == WE) begin
+    q_reg <= D;
+  end
+end
+
+// Wire q_reg to Q
+`ifndef ENABLE_FORMAL_VERIFICATION
+  assign Q = q_reg;
+  assign QN = ~q_reg;
+`else
+  assign Q = 1'bZ;
+  assign QN = !Q;
+`endif
+
+endmodule
+
+//-----------------------------------------------------
+// Function    : A Configurable Latch with
+//               - an active-high write enable signal
+//               - an active-high set signal
+//-----------------------------------------------------
+module LATCHS (
+  input SET, // Set signal
+  input WE, // Write enable
+  input D, // Data input
+  output Q, // Q output
+  output QN // Q negative output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ (SET or WE or D) begin
+  if (SET) begin
+    q_reg <= 1'b1;
+  end else if (1'b1 == WE) begin
+    q_reg <= D;
+  end
+end
+
+// Wire q_reg to Q
+`ifndef ENABLE_FORMAL_VERIFICATION
+  assign Q = q_reg;
+  assign QN = ~q_reg;
+`else
+  assign Q = 1'bZ;
+  assign QN = !Q;
+`endif
+
+endmodule
+
+//-----------------------------------------------------
+// Function    : A Configurable Latch with
+//               - an active-high write enable signal
+//               - an active-low set signal
+//-----------------------------------------------------
+module LATCHSN (
+  input SETN, // Set signal
+  input WE, // Write enable
+  input D, // Data input
+  output Q, // Q output
+  output QN // Q negative output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ (SETN or WE or D) begin
+  if (~SETN) begin
+    q_reg <= 1'b1;
+  end else if (1'b1 == WE) begin
+    q_reg <= D;
+  end
+end
+
+// Wire q_reg to Q
+`ifndef ENABLE_FORMAL_VERIFICATION
+  assign Q = q_reg;
+  assign QN = ~q_reg;
+`else
+  assign Q = 1'bZ;
+  assign QN = !Q;
+`endif
+
+endmodule
+
+//-----------------------------------------------------
+// Function    : A Configurable Latch with
+//               - an active-high write enable signal
+//               - an active-high reset signal
+//               - an active-high set signal
+//-----------------------------------------------------
+module LATCHSR (
+  input RST, // Reset signal
+  input SET, // Set signal
+  input WE, // Write enable
+  input D, // Data input
+  output Q, // Q output
+  output QN // Q negative output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ (RST or SET or WE or D) begin
+  if (RST) begin
+    q_reg <= 1'b0;
+  end else if (SET) begin
+    q_reg <= 1'b1;
+  end else if (1'b1 == WE) begin
+    q_reg <= D;
+  end
+end
+
+// Wire q_reg to Q
+`ifndef ENABLE_FORMAL_VERIFICATION
+  assign Q = q_reg;
+  assign QN = ~q_reg;
+`else
+  assign Q = 1'bZ;
+  assign QN = !Q;
+`endif
+
+endmodule
+
+//-----------------------------------------------------
+// Function    : A Configurable Latch with
+//               - an active-high write enable signal
+//               - an active-high reset signal
+//               - an active-high set signal
+//-----------------------------------------------------
+module LATCHSNRN (
+  input RSTN, // Reset signal
+  input SETN, // Set signal
+  input WE, // Write enable
+  input D, // Data input
+  output Q, // Q output
+  output QN // Q negative output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ (RSTN or SETN or WE or D) begin
+  if (~RSTN) begin
+    q_reg <= 1'b0;
+  end else if (~SETN) begin
+    q_reg <= 1'b1;
+  end else if (1'b1 == WE) begin
+    q_reg <= D;
+  end
+end
+
+// Wire q_reg to Q
+`ifndef ENABLE_FORMAL_VERIFICATION
+  assign Q = q_reg;
+  assign QN = ~q_reg;
+`else
+  assign Q = 1'bZ;
+  assign QN = !Q;
+`endif
+
+endmodule
+

openfpga_flow/VerilogNetlists/lb_tb.v

@@ -1,199 +0,0 @@
-//-----------------------------------------------------
-// Design Name : testbench for logic blocks
-// File Name   : lb_tb.v
-// Function    : Configurable logic block
-// Coder       : Xifan TANG
-//-----------------------------------------------------
-//----- Time scale: simulation time step and accuracy -----
-`timescale 1ns / 1ps
-
-module lb_tb;
-// Parameters
-parameter SIZE_IN = 40; //---- MUX input size 
-parameter SIZE_OUT = 10; //---- MUX input size 
-parameter SIZE_RESERV_BLWL = 49 + 1; //---- MUX input size 
-parameter SIZE_BLWL = 1019 - 310 + 1; //---- MUX input size 
-parameter prog_clk_period = 1; // [ns] half clock period
-parameter op_clk_period = 1; // [ns] half clock period
-parameter config_period =  2 * prog_clk_period; // [ns] One full clock period
-parameter operating_period =  SIZE_IN * 2 * op_clk_period; // [ns] One full clock period
-
-// Ports
-wire [0:SIZE_IN-1] lb_in;
-wire [0:SIZE_IN-1] lb_out;
-wire lb_clk;
-wire [0:SIZE_RESERV_BLWL-1] reserv_bl;
-wire [0:SIZE_RESERV_BLWL-1] reserv_wl;
-wire [0:SIZE_BLWL-1] bl;
-wire [0:SIZE_BLWL-1] wl;
-wire prog_EN;
-wire prog_ENb;
-wire zin;
-wire nequalize;
-wire read;
-wire clk;
-wire Reset;
-wire Set; 
-// Clocks
-wire prog_clock;
-wire op_clock;
-
-// Registered port
-reg [0:SIZE_IN-1] lb_in_reg;
-reg [0:SIZE_RESERV_BLWL-1] reserv_bl_reg;
-reg [0:SIZE_RESERV_BLWL-1] reserv_wl_reg;
-reg [0:SIZE_BLWL-1] bl_reg;
-reg [0:SIZE_BLWL-1] wl_reg;
-reg prog_clock_reg;
-reg op_clock_reg;
-
-// Config done signal;
-reg config_done;
-// Temp register for rotating shift
-reg temp;
-
-// Unit under test
-grid_1__1_ U0 (
-zin,
-nequalize,
-read,
-clk,
-Reset,
-Set,
-prog_ENb,
-prog_EN,
-// Top inputs
-lb_in[0], lb_in[4], lb_in[8], lb_in[12], lb_in[16], 
-lb_in[20], lb_in[24], lb_in[28], lb_in[32], lb_in[36], 
-// Top outputs
-lb_out[0], lb_out[4], lb_out[8], 
-// Right inputs
-lb_in[1], lb_in[5], lb_in[9], lb_in[13], lb_in[17], 
-lb_in[21], lb_in[25], lb_in[29], lb_in[33], lb_in[37], 
-// Right outputs
-lb_out[1], lb_out[5], lb_out[9], 
-// Bottom inputs
-lb_in[2], lb_in[6], lb_in[10], lb_in[14], lb_in[18], 
-lb_in[22], lb_in[26], lb_in[30], lb_in[34], lb_in[38], 
-// Bottom outputs
-lb_out[2], lb_out[6], 
-// Bottom inputs
-lb_clk, 
-// left inputs
-lb_in[3], lb_in[7], lb_in[11], lb_in[15], lb_in[19], 
-lb_in[23], lb_in[27], lb_in[31], lb_in[35], lb_in[39], 
-// left outputs
-lb_out[3], lb_out[7],  
-reserv_bl, reserv_wl,
-bl, wl 
-);
-
-// Task: assign BL and WL values 
-task prog_lb_blwl;
-  begin
-    @(posedge prog_clock);
-    // Rotate left shift
-    temp = reserv_bl_reg[SIZE_RESERV_BLWL-1];
-    //bl_reg = bl_reg >> 1;
-    reserv_bl_reg[1:SIZE_RESERV_BLWL-1] = reserv_bl_reg[0:SIZE_RESERV_BLWL-2]; 
-    reserv_bl_reg[0] = temp;
-  end 
-endtask
-
-// Task: assign inputs
-task op_lb_in;
-  begin
-    @(posedge op_clock);
-    temp = lb_in_reg[SIZE_IN-1];
-    lb_in_reg[1:SIZE_IN-1] = lb_in_reg[0:SIZE_IN-2];
-    lb_in_reg[0] = temp;
-  end 
-endtask
-
-// Configuration done signal
-initial
-begin
-  config_done = 1'b0;
-end
-// Enabled during config_period, Disabled during op_period 
-always
-begin
-  #config_period config_done = ~config_done;
-  #operating_period config_done = ~config_done;
-end
-
-// Programming clocks
-initial 
-begin
-  prog_clock_reg = 1'b0;
-end
-always
-begin
-  #prog_clk_period prog_clock_reg = ~prog_clock_reg; 
-end
-
-// Operating clocks
-initial 
-begin
-  op_clock_reg = 1'b0;
-end
-always
-begin
-  #op_clk_period op_clock_reg = ~op_clock_reg; 
-end
-
-// Programming and Operating clocks 
-assign prog_clock = prog_clock_reg & (~config_done);
-assign op_clock = op_clock_reg & config_done;
-
-// Programming Enable signals
-assign prog_EN = prog_clock & (~config_done);
-assign prog_ENb = ~prog_EN;
-
-// Programming phase: BL/WL 
-initial
-begin
-  // Initialize BL/WL registers
-  reserv_bl_reg = {SIZE_RESERV_BLWL {1'b0}}; 
-  reserv_bl_reg[0] = 1'b1;
-  reserv_wl_reg = {SIZE_RESERV_BLWL {1'b0}}; 
-  // Reserved BL/WL
-  bl_reg = {SIZE_BLWL {1'b0}};
-  wl_reg = {SIZE_BLWL {1'b1}};
-  //wl_reg[SIZE_BLWL-1] = 1'b1;
-end
-always wait (~config_done) // Only invoked when config_done is 0
-begin
-  // Propagate input 1 to the output
-  // BL[0] = 1, WL[4] = 1
-  prog_lb_blwl;
-end
-
-// Operating Phase
-initial
-begin
-  lb_in_reg = {SIZE_IN {1'b0}}; 
-  lb_in_reg[0] = 1'b1; // Last bit is 1 initially
-end
-always wait (config_done) // Only invoked when config_done is 1
-begin
-  /* Update inputs */
-  op_lb_in;
-end
-
-// Wire ports
-assign lb_in = lb_in_reg;
-assign reserv_bl = reserv_bl_reg;
-assign reserv_wl = reserv_wl_reg;
-assign bl = bl_reg;
-assign wl = wl_reg;
-
-// Constant ports
-assign zin = 1'b0;
-assign nequalize = 1'b1;
-assign read = 1'b0;
-assign clk = op_clock;
-assign Reset = ~config_done;
-assign Set = 1'b0; 
-
-endmodule

openfpga_flow/VerilogNetlists/sram.v

@@ -1,31 +1,31 @@
 //-----------------------------------------------------
 // Design Name : sram_blwl
 // File Name   : sram.v
-// Function    : A SRAM cell is is accessible
-//               when wl is enabled
 // Coder       : Xifan TANG
 //-----------------------------------------------------
-module sram_blwl(
-input reset, // Word line control signal
-input wl, // Word line control signal
-input bl, // Bit line control signal
-output out, // Data output
-output outb // Data output
+
+
+//-----------------------------------------------------
+// Function    : A SRAM cell with write enable
+//-----------------------------------------------------
+module SRAM(
+  input WE, // Word line control signal as write enable
+  input D, // Bit line control signal
+  output Q, // Data output
+  output QN // Data output
 );
 
   //----- local variable need to be registered
   reg data;
 
   //----- when wl is enabled, we can read in data from bl
-  always @(bl, wl) 
+  always @(WE or D) 
   begin
-    if (1'b1 == reset) begin 
-      data <= 1'b0;
-    end else if ((1'b1 == bl)&&(1'b1 == wl)) begin
+    if ((1'b1 == D)&&(1'b1 == WE)) begin
     //----- Cases to program internal memory bit 
     //----- case 1: bl = 1, wl = 1, a -> 0
       data <= 1'b1;
-    end else if ((1'b0 == bl)&&(1'b1 == wl)) begin
+    end else if ((1'b0 == D)&&(1'b1 == WE)) begin
     //----- case 2: bl = 0, wl = 1, a -> 0
      data <= 1'b0;
     end 
@@ -33,57 +33,276 @@ output outb // Data output
 
 `ifndef ENABLE_FORMAL_VERIFICATION
     // Wire q_reg to Q
-    assign out = data;
-    assign outb = ~data;
+    assign Q = data;
+    assign QN = ~data;
 `else
-    assign out = 1'bZ;
-    assign outb = !out;
+    assign Q = 1'bZ;
+    assign QN = !Q;
 `endif
 
 endmodule
 
-
-//------ Module: sram6T_blwl -----//
-//------ Verilog file: sram.v -----//
-//------ Author: Xifan TANG -----//
-module sram6T_blwl(
-//input read,
-//input nequalize,
-input din, // Data input
-output dout, // Data output
-output doutb, // Data output
-input bl, // Bit line control signal
-input wl, // Word line control signal
-input blb // Inverted Bit line control signal
+//-----------------------------------------------------
+// Function    : A SRAM cell with 
+//               - an active-high set
+//               - a write-enable
+//-----------------------------------------------------
+module SRAMS(
+  input SET, // active-high set signal
+  input WE, // Word line control signal as write enable
+  input D, // Bit line control signal as data input
+  output Q, // Data output
+  output QN // Data output
 );
+
   //----- local variable need to be registered
-  reg a;
+  reg data;
 
   //----- when wl is enabled, we can read in data from bl
-  always @(bl, wl) 
+  always @(D or WE) 
   begin
+    if (1'b1 == SET) begin 
+      data <= 1'b1;
+    end else if ((1'b1 == D)&&(1'b1 == WE)) begin
     //----- Cases to program internal memory bit 
     //----- case 1: bl = 1, wl = 1, a -> 0
-    if ((1'b1 == bl)&&(1'b1 == wl)) begin
-      a <= 1'b1;
-    end 
+      data <= 1'b1;
+    end else if ((1'b0 == D)&&(1'b1 == WE)) begin
     //----- case 2: bl = 0, wl = 1, a -> 0
-    if ((1'b0 == bl)&&(1'b1 == wl)) begin
-     a <= 1'b0;
+     data <= 1'b0;
     end 
   end
 
-  // dout is short-wired to din 
-  assign dout = a;
-  //---- doutb is always opposite to dout 
-  assign doutb = ~dout;
-`ifdef ENABLE_SIGNAL_INITIALIZATION
-   initial begin
-     $deposit(a, $random);
-   end
+`ifndef ENABLE_FORMAL_VERIFICATION
+    // Wire q_reg to Q
+    assign Q = data;
+    assign QN = ~data;
+`else
+    assign Q = 1'bZ;
+    assign QN = !Q;
 `endif
+
 endmodule
 
+//-----------------------------------------------------
+// Function    : A SRAM cell with 
+//               - an active-low set
+//               - a write-enable
+//-----------------------------------------------------
+module SRAMSN(
+  input SETN, // active-low set signal
+  input WE, // Word line control signal as write enable
+  input D, // Bit line control signal as data input
+  output Q, // Data output
+  output QN // Data output
+);
+
+  //----- local variable need to be registered
+  reg data;
+
+  //----- when wl is enabled, we can read in data from bl
+  always @(D or WE) 
+  begin
+    if (1'b0 == SETN) begin 
+      data <= 1'b1;
+    end else if ((1'b1 == D)&&(1'b1 == WE)) begin
+    //----- Cases to program internal memory bit 
+    //----- case 1: bl = 1, wl = 1, a -> 0
+      data <= 1'b1;
+    end else if ((1'b0 == D)&&(1'b1 == WE)) begin
+    //----- case 2: bl = 0, wl = 1, a -> 0
+     data <= 1'b0;
+    end 
+  end
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+    // Wire q_reg to Q
+    assign Q = data;
+    assign QN = ~data;
+`else
+    assign Q = 1'bZ;
+    assign QN = !Q;
+`endif
+
+endmodule
+
+//-----------------------------------------------------
+// Function    : A SRAM cell with 
+//               - an active-high reset
+//               - a write-enable
+//-----------------------------------------------------
+module SRAMR(
+  input RST, // active-high reset signal
+  input WE, // Word line control signal as write enable
+  input D, // Bit line control signal as data input
+  output Q, // Data output
+  output QN // Data output
+);
+
+  //----- local variable need to be registered
+  reg data;
+
+  //----- when wl is enabled, we can read in data from bl
+  always @(D or WE) 
+  begin
+    if (1'b1 == RST) begin 
+      data <= 1'b0;
+    end else if ((1'b1 == D)&&(1'b1 == WE)) begin
+    //----- Cases to program internal memory bit 
+    //----- case 1: bl = 1, wl = 1, a -> 0
+      data <= 1'b1;
+    end else if ((1'b0 == D)&&(1'b1 == WE)) begin
+    //----- case 2: bl = 0, wl = 1, a -> 0
+     data <= 1'b0;
+    end 
+  end
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+    // Wire q_reg to Q
+    assign Q = data;
+    assign QN = ~data;
+`else
+    assign Q = 1'bZ;
+    assign QN = !Q;
+`endif
+
+endmodule
+
+//-----------------------------------------------------
+// Function    : A SRAM cell with 
+//               - an active-low reset
+//               - a write-enable
+//-----------------------------------------------------
+module SRAMRN(
+  input RSTN, // active-low reset signal
+  input WE, // Word line control signal as write enable
+  input D, // Bit line control signal as data input
+  output Q, // Data output
+  output QN // Data output
+);
+
+  //----- local variable need to be registered
+  reg data;
+
+  //----- when wl is enabled, we can read in data from bl
+  always @(D or WE) 
+  begin
+    if (1'b0 == RSTN) begin 
+      data <= 1'b0;
+    end else if ((1'b1 == D)&&(1'b1 == WE)) begin
+    //----- Cases to program internal memory bit 
+    //----- case 1: bl = 1, wl = 1, a -> 0
+      data <= 1'b1;
+    end else if ((1'b0 == D)&&(1'b1 == WE)) begin
+    //----- case 2: bl = 0, wl = 1, a -> 0
+     data <= 1'b0;
+    end 
+  end
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+    // Wire q_reg to Q
+    assign Q = data;
+    assign QN = ~data;
+`else
+    assign Q = 1'bZ;
+    assign QN = !Q;
+`endif
+
+endmodule
+
+//-----------------------------------------------------
+// Function    : A SRAM cell with 
+//               - an active-high reset
+//               - an active-high set
+//               - a write-enable
+//-----------------------------------------------------
+module SRAMSR(
+  input RST, // active-high reset signal
+  input SET, // active-high set signal
+  input WE, // Word line control signal as write enable
+  input D, // Bit line control signal as data input
+  output Q, // Data output
+  output QN // Data output
+);
+
+  //----- local variable need to be registered
+  reg data;
+
+  //----- when wl is enabled, we can read in data from bl
+  always @(D or WE) 
+  begin
+    if (1'b1 == RST) begin 
+      data <= 1'b0;
+    end else if (1'b1 == SET) begin 
+      data <= 1'b1;
+    end else if ((1'b1 == D)&&(1'b1 == WE)) begin
+    //----- Cases to program internal memory bit 
+    //----- case 1: bl = 1, wl = 1, a -> 0
+      data <= 1'b1;
+    end else if ((1'b0 == D)&&(1'b1 == WE)) begin
+    //----- case 2: bl = 0, wl = 1, a -> 0
+     data <= 1'b0;
+    end 
+  end
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+    // Wire q_reg to Q
+    assign Q = data;
+    assign QN = ~data;
+`else
+    assign Q = 1'bZ;
+    assign QN = !Q;
+`endif
+
+endmodule
+
+//-----------------------------------------------------
+// Function    : A SRAM cell with 
+//               - an active-low reset
+//               - an active-low set
+//               - a write-enable
+//-----------------------------------------------------
+module SRAMSNRN(
+  input RSTN, // active-low reset signal
+  input SETN, // active-low set signal
+  input WE, // Word line control signal as write enable
+  input D, // Bit line control signal as data input
+  output Q, // Data output
+  output QN // Data output
+);
+
+  //----- local variable need to be registered
+  reg data;
+
+  //----- when wl is enabled, we can read in data from bl
+  always @(D or WE) 
+  begin
+    if (1'b0 == RSTN) begin 
+      data <= 1'b0;
+    end else if (1'b0 == SETN) begin 
+      data <= 1'b1;
+    end else if ((1'b1 == D)&&(1'b1 == WE)) begin
+    //----- Cases to program internal memory bit 
+    //----- case 1: bl = 1, wl = 1, a -> 0
+      data <= 1'b1;
+    end else if ((1'b0 == D)&&(1'b1 == WE)) begin
+    //----- case 2: bl = 0, wl = 1, a -> 0
+     data <= 1'b0;
+    end 
+  end
+
+`ifndef ENABLE_FORMAL_VERIFICATION
+    // Wire q_reg to Q
+    assign Q = data;
+    assign QN = ~data;
+`else
+    assign Q = 1'bZ;
+    assign QN = !Q;
+`endif
+
+endmodule
+
+
 module sram6T_rram(
 input read,
 input nequalize,

openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml

@@ -124,15 +124,15 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="input" prefix="D" lib_name="D" size="1"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
     <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
       <design_technology type="cmos"/>
@@ -146,28 +146,27 @@
       <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="sram" name="sram_blwl" prefix="sram_blwl" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
+    <circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="bl" prefix="bl" size="1"/>
-       <port type="wl" prefix="wl" size="1"/>
-       <port type="output" prefix="out" size="1"/>
-       <port type="output" prefix="outb" size="1"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="out" lib_name="Q" size="1"/>
+       <port type="output" prefix="outb" lib_name="QN" size="1"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sram_blwl" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="SRAM" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="memory_bank" circuit_model_name="sram_blwl"/>
+    <organization type="memory_bank" circuit_model_name="SRAM"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
@@ -181,7 +180,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -193,7 +192,7 @@
       <interconnect name="crossbar" circuit_model_name="mux_2level"/>
     </pb_type>
     <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
-    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml

@@ -30,6 +30,7 @@
   <circuit_library>
     <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
       <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -41,6 +42,7 @@
     </circuit_model>
     <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
       <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -52,6 +54,7 @@
     </circuit_model>
     <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
       <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -63,6 +66,7 @@
     </circuit_model>
     <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
       <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
       <input_buffer exist="false"/>
       <output_buffer exist="false"/>
       <port type="input" prefix="in" size="1"/>
@@ -120,50 +124,51 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
-    <circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
       <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
       <lut_input_buffer exist="true" circuit_model_name="buf4"/>
       <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="6"/>
+      <port type="input" prefix="in" size="4"/>
       <port type="output" prefix="out" size="1"/>
-      <port type="sram" prefix="sram" size="64"/>
+      <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="sram" name="SRAMSR" prefix="SRAMSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="out" lib_name="Q" size="1"/>
+       <port type="output" prefix="outb" lib_name="QN" size="1"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="SRAMSR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+    <organization type="memory_bank" circuit_model_name="SRAMSR"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
@@ -177,7 +182,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -188,41 +193,8 @@
       <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
       <interconnect name="crossbar" circuit_model_name="mux_2level"/>
     </pb_type>
-    <pb_type name="clb.fle[n1_lut6].ble6.lut6" circuit_model_name="lut6"/>
-    <pb_type name="clb.fle[n1_lut6].ble6.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>

openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml

@@ -30,6 +30,7 @@
   <circuit_library>
     <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
       <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -41,6 +42,7 @@
     </circuit_model>
     <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
       <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -52,6 +54,7 @@
     </circuit_model>
     <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
       <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -61,22 +64,9 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
-      <design_technology type="cmos" topology="OR"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
     <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
       <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
       <input_buffer exist="false"/>
       <output_buffer exist="false"/>
       <port type="input" prefix="in" size="1"/>
@@ -134,53 +124,50 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
-    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
       <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
       <lut_input_buffer exist="true" circuit_model_name="buf4"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
       <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
-      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="64"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="sram" name="SRAMR" prefix="SRAMR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="out" lib_name="Q" size="1"/>
+       <port type="output" prefix="outb" lib_name="QN" size="1"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="SRAMR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+    <organization type="memory_bank" circuit_model_name="SRAMR"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
@@ -194,7 +181,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -205,56 +192,8 @@
       <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
       <interconnect name="crossbar" circuit_model_name="mux_2level"/>
     </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:4]"/>
-      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
-      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:5]"/>
-      <port name="out" physical_mode_port="lut6_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>

openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml

@@ -30,6 +30,7 @@
   <circuit_library>
     <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
       <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -41,6 +42,7 @@
     </circuit_model>
     <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
       <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -52,6 +54,7 @@
     </circuit_model>
     <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
       <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -61,22 +64,9 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
-      <design_technology type="cmos" topology="OR"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
     <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
       <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
       <input_buffer exist="false"/>
       <output_buffer exist="false"/>
       <port type="input" prefix="in" size="1"/>
@@ -134,57 +124,50 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
-    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
       <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
       <lut_input_buffer exist="true" circuit_model_name="buf4"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
       <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
-      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="64"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="sram" name="SRAMRN" prefix="SRAMRN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="RSTN" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="out" lib_name="Q" size="1"/>
+       <port type="output" prefix="outb" lib_name="QN" size="1"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true" />
-      <!-- A spypad for the direction port of the I/O pad, which can be visible in the fpga_top -->
-      <port type="input" prefix="din" size="1" is_global="true" is_io="true" default_value="0"/>
-      <port type="output" prefix="dout" size="1" is_global="true" is_io="true"/>
-      <port type="output" prefix="dir" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="SRAMRN" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+    <organization type="memory_bank" circuit_model_name="SRAMRN"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
@@ -198,7 +181,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -209,56 +192,8 @@
       <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
       <interconnect name="crossbar" circuit_model_name="mux_2level"/>
     </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:4]"/>
-      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
-      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:5]"/>
-      <port name="out" physical_mode_port="lut6_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>

openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml

@@ -0,0 +1,199 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="sram" name="SRAMS" prefix="SRAMS" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="out" lib_name="Q" size="1"/>
+       <port type="output" prefix="outb" lib_name="QN" size="1"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="SRAMS" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="memory_bank" circuit_model_name="SRAMS"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml

@@ -0,0 +1,199 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="sram" name="SRAMSN" prefix="SRAMSN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sram.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pSet" lib_name="SETN" size="1" is_global="true" default_val="1" is_set="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="out" lib_name="Q" size="1"/>
+       <port type="output" prefix="outb" lib_name="QN" size="1"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="SRAMSN" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="memory_bank" circuit_model_name="SRAMSN"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml

@@ -115,15 +115,15 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
     <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
       <design_technology type="cmos"/>
@@ -137,28 +137,27 @@
       <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ccff" name="DFF" prefix="DFF" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="output" prefix="QN" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFF" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+    <organization type="scan_chain" circuit_model_name="DFF"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
@@ -172,7 +171,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -184,7 +183,7 @@
       <interconnect name="crossbar" circuit_model_name="mux_tree"/>
     </pb_type>
     <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
-    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml

@@ -30,6 +30,7 @@
   <circuit_library>
     <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
       <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -41,6 +42,7 @@
     </circuit_model>
     <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
       <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -52,6 +54,7 @@
     </circuit_model>
     <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
       <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -61,22 +64,9 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
-      <design_technology type="cmos" topology="OR"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
-    <circuit_model type="pass_gate" name="MUX2" prefix="MUX2" is_default="true">
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
       <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
       <input_buffer exist="false"/>
       <output_buffer exist="false"/>
       <port type="input" prefix="in" size="1"/>
@@ -106,72 +96,70 @@
       <port type="output" prefix="out" size="1"/>
       <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
     </circuit_model>
-    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
+    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
       <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="MUX2"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
-    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
+    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" is_default="true" dump_structural_verilog="true">
       <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="MUX2"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
-    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
       <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
       <lut_input_buffer exist="true" circuit_model_name="buf4"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
-      <pass_gate_logic circuit_model_name="MUX2"/>
-      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
-      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="64"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ccff" name="DFFSR" prefix="DFFSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="output" prefix="QN" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFSR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+    <organization type="scan_chain" circuit_model_name="DFFSR"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
@@ -185,7 +173,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -196,56 +184,8 @@
       <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
       <interconnect name="crossbar" circuit_model_name="mux_tree"/>
     </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:4]"/>
-      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
-      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:5]"/>
-      <port name="out" physical_mode_port="lut6_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>

openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml

@@ -30,6 +30,7 @@
   <circuit_library>
     <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
       <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -41,6 +42,7 @@
     </circuit_model>
     <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
       <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -52,6 +54,7 @@
     </circuit_model>
     <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
       <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -61,36 +64,22 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
-      <design_technology type="cmos" topology="OR"/>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
       <input_buffer exist="false"/>
       <output_buffer exist="false"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
       <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
       </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
       </delay_matrix>
     </circuit_model>
-    <!-- Define a circuit model for the standard cell MUX2 
-         OpenFPGA requires the following truth table for the MUX2
-         When the select signal sel is enabled, the first input, i.e., in0 
-         will be propagated to the output, i.e., out
-         If your standard cell provider does not offer the exact truth table,
-         you can simply swap the inputs as shown in the example below
-      -->
-    <circuit_model type="gate" name="stdcell_mux2" prefix="stdcell_mux2" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/sc_mux2.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/sc_mux2.v">
-      <design_technology type="cmos" topology="MUX2"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="in0" lib_name="B" size="1"/>
-      <port type="input" prefix="in1" lib_name="A" size="1"/>
-      <port type="input" prefix="sel" lib_name="S" size="1"/>
-      <port type="output" prefix="out" lib_name="Y" size="1"/>
-    </circuit_model>
     <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
       <design_technology type="cmos"/>
       <input_buffer exist="false"/>
@@ -107,72 +96,69 @@
       <port type="output" prefix="out" size="1"/>
       <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
     </circuit_model>
-    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" is_default="true" dump_structural_verilog="true">
+    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
       <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <pass_gate_logic circuit_model_name="stdcell_mux2"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
-    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" dump_structural_verilog="true">
+    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" is_default="true" dump_structural_verilog="true">
       <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="tap_buf4"/>
-      <pass_gate_logic circuit_model_name="stdcell_mux2"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
-    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
       <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
       <lut_input_buffer exist="true" circuit_model_name="buf4"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
-      <pass_gate_logic circuit_model_name="stdcell_mux2"/>
-      <port type="input" prefix="in" size="6" tri_state_map="-----1" circuit_model_name="OR2"/>
-      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="64"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="output" prefix="QN" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+    <organization type="scan_chain" circuit_model_name="DFFR"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
@@ -186,7 +172,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -197,56 +183,8 @@
       <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
       <interconnect name="crossbar" circuit_model_name="mux_tree"/>
     </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="1" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:4]"/>
-      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut5].lut5inter.ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="0">
-      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:5]"/>
-      <port name="out" physical_mode_port="lut6_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>

openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml

@@ -0,0 +1,190 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="DFFRN" prefix="DFFRN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="RSTN" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="QN" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFRN" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="DFFRN"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_tree_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_tree"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml

@@ -0,0 +1,190 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="DFFS" prefix="DFFS" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="QN" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFS" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="DFFS"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_tree_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_tree"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml

@@ -0,0 +1,190 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree" prefix="mux_tree" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_tree_tapbuf" prefix="mux_tree_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="tree" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ccff" name="DFFSN" prefix="DFFSN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pSet" lib_name="SETN" size="1" is_global="true" default_val="1" is_set="true" is_prog="true"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="output" prefix="QN" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFSN" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="scan_chain" circuit_model_name="DFFSN"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_tree_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_tree_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_tree"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml

@@ -124,15 +124,15 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
     <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
       <design_technology type="cmos"/>
@@ -146,28 +146,28 @@
       <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="output" prefix="QN" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+    <organization type="scan_chain" circuit_model_name="DFFR"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
@@ -181,7 +181,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -193,7 +193,7 @@
       <interconnect name="crossbar" circuit_model_name="mux_2level"/>
     </pb_type>
     <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
-    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml

@@ -30,6 +30,7 @@
   <circuit_library>
     <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
       <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -41,6 +42,7 @@
     </circuit_model>
     <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
       <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -52,6 +54,7 @@
     </circuit_model>
     <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
       <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -61,22 +64,9 @@
         10e-12
       </delay_matrix>
     </circuit_model>
-    <circuit_model type="gate" name="OR2" prefix="OR2" is_default="true">
-      <design_technology type="cmos" topology="OR"/>
-      <input_buffer exist="false"/>
-      <output_buffer exist="false"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="output" prefix="out" size="1"/>
-      <delay_matrix type="rise" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-      <delay_matrix type="fall" in_port="a b" out_port="out">
-        10e-12 5e-12
-      </delay_matrix>
-    </circuit_model>
     <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
       <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
       <input_buffer exist="false"/>
       <output_buffer exist="false"/>
       <port type="input" prefix="in" size="1"/>
@@ -134,64 +124,50 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
-    <circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
-      <design_technology type="cmos" fracturable_lut="true"/>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
       <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
       <lut_input_buffer exist="true" circuit_model_name="buf4"/>
-      <lut_intermediate_buffer exist="true" circuit_model_name="buf4" location_map="-1-1-"/>
       <pass_gate_logic circuit_model_name="TGATE"/>
-      <port type="input" prefix="in" size="6" tri_state_map="----11" circuit_model_name="OR2"/>
-      <port type="output" prefix="lut4_out" size="4" lut_frac_level="4" lut_output_mask="0,1,2,3"/>
-      <port type="output" prefix="lut5_out" size="2" lut_frac_level="5" lut_output_mask="0,1"/>
-      <port type="output" prefix="lut6_out" size="1" lut_output_mask="0"/>
-      <port type="sram" prefix="sram" size="64"/>
-      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="sram" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="input" prefix="D" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="CK" size="1" is_edge_triggered="true"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="output" prefix="Qb" lib_name="QN" size="1"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
-    </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
-      <design_technology type="cmos"/>
-      <input_buffer exist="true" circuit_model_name="INVTX1"/>
-      <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="input" prefix="cin" size="1"/>
-      <port type="output" prefix="sumout" size="1"/>
-      <port type="output" prefix="cout" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+    <organization type="frame_based" circuit_model_name="DFFR"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
@@ -202,13 +178,10 @@
   <routing_segment>
     <segment name="L4" circuit_model_name="chan_segment"/>
   </routing_segment>
-  <direct_connection>
-    <direct name="adder_carry" circuit_model_name="direct_interc"/>
-  </direct_connection>
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -219,67 +192,8 @@
       <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
       <interconnect name="crossbar" circuit_model_name="mux_2level"/>
     </pb_type>
-    <pb_type name="clb.fle" physical_mode_name="physical"/>
-    <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut6" circuit_model_name="frac_lut6" mode_bits="11"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
-    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
-    <!-- Binding operating pb_type to physical pb_type -->
-    <!-- Binding operating pb_types in mode 'n2_lut5' -->
-    <pb_type name="clb.fle[n2_lut5].ble5.lut5" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="01" physical_pb_type_index_factor="0.5">
-      <!-- Binding the lut5 to the first 5 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:4]"/>
-      <port name="out" physical_mode_port="lut5_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[n2_lut5].ble5.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'arithmetic' -->
-    <pb_type name="clb.fle[arithmetic].arithmetic.lut4" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="11" physical_pb_type_index_factor="0.25">
-      <!-- Binding the lut4 to the first 4 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:3]"/>
-      <port name="out" physical_mode_port="lut4_out[0:0]" physical_mode_pin_rotate_offset="1"/>
-    </pb_type>
-    <pb_type name="clb.fle[arithmetic].arithmetic.adder" physical_pb_type_name="clb.fle[physical].fabric.adder"/>
-    <pb_type name="clb.fle[arithmetic].arithmetic.ff" physical_pb_type_name="clb.fle[physical].fabric.ff"/>
-    <!-- Binding operating pb_types in mode 'ble6' -->
-    <pb_type name="clb.fle[n1_lut6].ble6.lut6" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut6" mode_bits="00">
-      <!-- Binding the lut6 to the first 6 inputs of fracturable lut6 -->
-      <port name="in" physical_mode_port="in[0:5]"/>
-      <port name="out" physical_mode_port="lut6_out"/>
-    </pb_type>
-    <pb_type name="clb.fle[n1_lut6].ble6.ff" physical_pb_type_name="clb.fle[physical].fabric.ff" physical_pb_type_index_factor="2" physical_pb_type_index_offset="0"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>
-<openfpga_simulation_setting>
-  <clock_setting>
-    <!--operating frequency="auto" num_cycles="auto" slack="0.2"/-->
-    <operating frequency="200e6" num_cycles="auto" slack="0.2"/>
-    <programming frequency="10e6"/>
-  </clock_setting>
-  <simulator_option>
-    <operating_condition temperature="25"/>
-    <output_log verbose="false" captab="false"/>
-    <accuracy type="abs" value="1e-13"/>
-    <runtime fast_simulation="true"/>
-  </simulator_option>
-  <monte_carlo num_simulation_points="2"/>
-  <measurement_setting>
-    <slew>
-      <rise upper_thres_pct="0.95" lower_thres_pct="0.05"/>
-      <fall upper_thres_pct="0.05" lower_thres_pct="0.95"/>
-    </slew>
-    <delay>
-      <rise input_thres_pct="0.5" output_thres_pct="0.5"/>
-      <fall input_thres_pct="0.5" output_thres_pct="0.5"/>
-    </delay>
-  </measurement_setting>
-  <stimulus>
-    <clock>
-      <rise slew_type="abs" slew_time="20e-12" />
-      <fall slew_type="abs" slew_time="20e-12" />
-    </clock>
-    <input>
-      <rise slew_type="abs" slew_time="25e-12" />
-      <fall slew_type="abs" slew_time="25e-12" />
-    </input>
-  </stimulus>
-</openfpga_simulation_setting>

openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml

@@ -124,15 +124,15 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
     <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
       <design_technology type="cmos"/>
@@ -146,29 +146,27 @@
       <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
+    <circuit_model type="sram" name="LATCH" prefix="LATCH" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="bl" prefix="bl" size="1"/>
-       <port type="wl" prefix="wl" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="output" prefix="Qb" lib_name="QN" size="1"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="LATCH" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="frame_based" circuit_model_name="config_latch"/>
+    <organization type="frame_based" circuit_model_name="LATCH"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
@@ -182,7 +180,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -194,7 +192,7 @@
       <interconnect name="crossbar" circuit_model_name="mux_2level"/>
     </pb_type>
     <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
-    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml

@@ -0,0 +1,202 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="sram" name="SDFFSR" prefix="SDFFSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="CK" size="1" is_edge_triggered="true"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="output" prefix="Qb" lib_name="QN" size="1"/>
+       <port type="input" prefix="SE" lib_name="SE" size="1" is_global="true" default_val="0"/>
+       <port type="input" prefix="SI" lib_name="SI" size="1" is_global="true" default_val="0"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="SDFFSR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="frame_based" circuit_model_name="SDFFSR"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml

@@ -0,0 +1,200 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="sram" name="LATCHSR" prefix="LATCHSR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="output" prefix="Qb" lib_name="QN" size="1"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="LATCHSR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="frame_based" circuit_model_name="LATCHSR"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml

@@ -0,0 +1,199 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="output" prefix="Qb" lib_name="QN" size="1"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="frame_based" circuit_model_name="LATCHR"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml

@@ -0,0 +1,199 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="sram" name="LATCHRN" prefix="LATCHRN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="RSTN" size="1" is_global="true" default_val="1" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="output" prefix="Qb" lib_name="QN" size="1"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="LATCHRN" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="frame_based" circuit_model_name="LATCHRN"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml

@@ -0,0 +1,199 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="sram" name="LATCHS" prefix="LATCHS" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pSet" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="output" prefix="Qb" lib_name="QN" size="1"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="LATCHS" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="frame_based" circuit_model_name="LATCHS"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml

@@ -0,0 +1,199 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="sram" name="LATCHSN" prefix="LATCHSN" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pSet" lib_name="SETN" size="1" is_global="true" default_val="1" is_set="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="output" prefix="Qb" lib_name="QN" size="1"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="LATCHSN" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="frame_based" circuit_model_name="LATCHSN"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml

@@ -36,7 +36,7 @@
       <design_technology type="cmos" power_gated="true" topology="inverter" size="1"/>
       <device_technology device_model_name="logic"/>
       <port type="input" prefix="in" size="1"/>
-      <port type="input" prefix="en" size="1" is_global="true" default_val="0" is_config_enable="true"/>
+      <port type="input" prefix="DIR" size="1" is_global="true" default_val="0" is_config_enable="true"/>
       <port type="input" prefix="enb" size="1" is_global="true" default_val="1" is_config_enable="true"/>
       <port type="output" prefix="out" size="1"/>
       <delay_matrix type="rise" in_port="in" out_port="out">
@@ -130,15 +130,15 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
     <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
       <design_technology type="cmos"/>
@@ -152,29 +152,28 @@
       <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
+    <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="bl" prefix="bl" size="1"/>
-       <port type="wl" prefix="wl" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="output" prefix="Qb" lib_name="QN" size="1"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="frame_based" circuit_model_name="config_latch"/>
+    <organization type="frame_based" circuit_model_name="LATCHR"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
@@ -188,7 +187,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -200,7 +199,7 @@
       <interconnect name="crossbar" circuit_model_name="mux_2level"/>
     </pb_type>
     <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
-    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml

@@ -124,15 +124,15 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
     <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
       <design_technology type="cmos"/>
@@ -146,29 +146,28 @@
       <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
+    <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="bl" prefix="bl" size="1"/>
-       <port type="wl" prefix="wl" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="output" prefix="Qb" lib_name="QN" size="1"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="standalone" circuit_model_name="config_latch"/>
+    <organization type="standalone" circuit_model_name="LATCHR"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
@@ -182,7 +181,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -194,7 +193,7 @@
       <interconnect name="crossbar" circuit_model_name="mux_2level"/>
     </pb_type>
     <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
-    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml

@@ -124,15 +124,15 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
     <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
       <design_technology type="cmos"/>
@@ -146,29 +146,28 @@
       <port type="sram" prefix="sram" size="16"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
+    <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="bl" prefix="bl" size="1"/>
-       <port type="wl" prefix="wl" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="output" prefix="Qb" lib_name="QN" size="1"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="frame_based" circuit_model_name="config_latch"/>
+    <organization type="frame_based" circuit_model_name="LATCHR"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
@@ -182,7 +181,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -190,7 +189,7 @@
     <!-- physical pb_type binding in complex block CLB -->
     <!-- physical mode will be the default mode if not specified -->
     <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
-    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>

openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml

@@ -0,0 +1,212 @@
+<!-- Architecture annotation for OpenFPGA framework
+     This annotation supports the k6_N10_40nm.xml 
+     - General purpose logic block
+       - K = 6, N = 10, I = 40
+       - Single mode
+     - Routing architecture
+       - L = 4, fc_in = 0.15, fc_out = 0.1
+  -->
+<openfpga_architecture>
+  <technology_library>
+    <device_library>
+      <device_model name="logic" type="transistor">
+        <lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="0.9" pn_ratio="2"/>
+        <pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+        <nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
+      </device_model>
+      <device_model name="io" type="transistor">
+        <lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
+        <design vdd="2.5" pn_ratio="3"/>
+        <pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+        <nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
+      </device_model>
+    </device_library>
+    <variation_library>
+      <variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+      <variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
+    </variation_library>
+  </technology_library>
+  <circuit_library>
+    <circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
+      <design_technology type="cmos" topology="inverter" size="1"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
+      <design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
+      <device_technology device_model_name="logic"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in" out_port="out">
+        10e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
+      <design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
+      <device_technology device_model_name="logic"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="input" prefix="sel" size="1"/>
+      <port type="input" prefix="selb" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <delay_matrix type="rise" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+      <delay_matrix type="fall" in_port="in sel selb" out_port="out">
+        10e-12 5e-12 5e-12
+      </delay_matrix>
+    </circuit_model>
+    <circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
+    </circuit_model>
+    <circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="false"/>
+      <output_buffer exist="false"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
+      <design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="tap_buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="1"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="1"/>
+    </circuit_model>
+    <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="D" size="1"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="output" prefix="Q" size="1"/>
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
+    </circuit_model>
+    <circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
+      <lut_input_buffer exist="true" circuit_model_name="buf4"/>
+      <pass_gate_logic circuit_model_name="TGATE"/>
+      <port type="input" prefix="in" size="4"/>
+      <port type="output" prefix="out" size="1"/>
+      <port type="sram" prefix="sram" size="16"/>
+    </circuit_model>
+    <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
+    <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
+       <design_technology type="cmos"/>
+       <input_buffer exist="true" circuit_model_name="INVTX1"/>
+       <output_buffer exist="true" circuit_model_name="INVTX1"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="output" prefix="Qb" lib_name="QN" size="1"/>
+    </circuit_model>
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
+      <design_technology type="cmos"/>
+      <input_buffer exist="true" circuit_model_name="INVTX1"/>
+      <output_buffer exist="true" circuit_model_name="INVTX1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
+    </circuit_model>
+  </circuit_library>
+  <configuration_protocol>
+    <organization type="frame_based" circuit_model_name="LATCHR"/>
+  </configuration_protocol>
+  <connection_block>
+    <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
+  </connection_block>
+  <switch_block>
+    <switch name="0" circuit_model_name="mux_2level_tapbuf"/>
+  </switch_block>
+  <routing_segment>
+    <segment name="L4" circuit_model_name="chan_segment"/>
+  </routing_segment>
+  <pb_type_annotations>
+    <!-- physical pb_type binding in complex block IO -->
+    <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
+    <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
+    <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
+    <!-- End physical pb_type binding in complex block IO -->
+
+    <!-- physical pb_type binding in complex block CLB -->
+    <!-- physical mode will be the default mode if not specified -->
+    <pb_type name="clb">
+      <!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
+      <interconnect name="crossbar_fle0" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar_fle1_in0" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar_fle1" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar_fle2_in0" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar_fle2_in1" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar_fle2" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar_fle3_in0" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar_fle3_in1" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar_fle3_in2" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar_fle3" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar_fle4_in0" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar_fle4_in1" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar_fle4_in2" circuit_model_name="mux_2level"/>
+      <interconnect name="crossbar_fle4_in3" circuit_model_name="mux_2level"/>
+    </pb_type>
+    <pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
+    <pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
+    <!-- End physical pb_type binding in complex block IO -->
+  </pb_type_annotations>
+</openfpga_architecture>

openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml

@@ -139,15 +139,15 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
     <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
       <design_technology type="cmos" fracturable_lut="true"/>
@@ -161,31 +161,31 @@
       <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
       <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
       <port type="sram" prefix="sram" size="16"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="output" prefix="QN" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+    <organization type="scan_chain" circuit_model_name="DFFR"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
@@ -199,7 +199,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -212,7 +212,7 @@
     </pb_type>
     <pb_type name="clb.fle" physical_mode_name="physical"/>
     <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
     <!-- Binding operating pb_type to physical pb_type -->
     <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
       <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->

openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml

@@ -139,15 +139,15 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
     <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
       <design_technology type="cmos" fracturable_lut="true"/>
@@ -161,41 +161,41 @@
       <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
       <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
       <port type="sram" prefix="sram" size="16"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="output" prefix="QN" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+    <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="input" prefix="cin" size="1"/>
-      <port type="output" prefix="sumout" size="1"/>
-      <port type="output" prefix="cout" size="1"/>
+      <port type="input" prefix="a" lib_name="A" size="1"/>
+      <port type="input" prefix="b" lib_name="B" size="1"/>
+      <port type="input" prefix="cin" lib_name="CI" size="1"/>
+      <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
+      <port type="output" prefix="cout" lib_name="CO" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+    <organization type="scan_chain" circuit_model_name="DFFR"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
@@ -212,7 +212,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -225,8 +225,8 @@
     </pb_type>
     <pb_type name="clb.fle" physical_mode_name="physical"/>
     <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
-    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
     <!-- Binding operating pb_type to physical pb_type -->
     <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
       <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->

openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml

@@ -139,15 +139,15 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
     <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
       <design_technology type="cmos" fracturable_lut="true"/>
@@ -161,38 +161,37 @@
       <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
       <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
       <port type="sram" prefix="sram" size="16"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
+    <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="bl" prefix="bl" size="1"/>
-       <port type="wl" prefix="wl" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="output" prefix="Qb" lib_name="QN" size="1"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+    <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="input" prefix="cin" size="1"/>
-      <port type="output" prefix="sumout" size="1"/>
-      <port type="output" prefix="cout" size="1"/>
+      <port type="input" prefix="a" lib_name="A" size="1"/>
+      <port type="input" prefix="b" lib_name="B" size="1"/>
+      <port type="input" prefix="cin" lib_name="CI" size="1"/>
+      <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
+      <port type="output" prefix="cout" lib_name="CO" size="1"/>
     </circuit_model>
     <circuit_model type="hard_logic" name="dpram_128x8" prefix="dpram_128x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram1k.v">
       <design_technology type="cmos"/>
@@ -208,7 +207,7 @@
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="frame_based" circuit_model_name="config_latch"/>
+    <organization type="frame_based" circuit_model_name="LATCHR"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
@@ -225,7 +224,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -238,8 +237,8 @@
     </pb_type>
     <pb_type name="clb.fle" physical_mode_name="physical"/>
     <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
-    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
     <!-- Binding operating pb_type to physical pb_type -->
     <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
       <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->

openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml

@@ -139,15 +139,15 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
     <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
       <design_technology type="cmos" fracturable_lut="true"/>
@@ -161,38 +161,37 @@
       <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
       <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
       <port type="sram" prefix="sram" size="16"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
+    <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="bl" prefix="bl" size="1"/>
-       <port type="wl" prefix="wl" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="output" prefix="Qb" lib_name="QN" size="1"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+    <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="input" prefix="cin" size="1"/>
-      <port type="output" prefix="sumout" size="1"/>
-      <port type="output" prefix="cout" size="1"/>
+      <port type="input" prefix="a" lib_name="A" size="1"/>
+      <port type="input" prefix="b" lib_name="B" size="1"/>
+      <port type="input" prefix="cin" lib_name="CI" size="1"/>
+      <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
+      <port type="output" prefix="cout" lib_name="CO" size="1"/>
     </circuit_model>
     <circuit_model type="hard_logic" name="dpram_128x8" prefix="dpram_128x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram1k.v">
       <design_technology type="cmos"/>
@@ -208,7 +207,7 @@
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="frame_based" circuit_model_name="config_latch"/>
+    <organization type="frame_based" circuit_model_name="LATCHR"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
@@ -229,7 +228,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -242,8 +241,8 @@
     </pb_type>
     <pb_type name="clb.fle" physical_mode_name="physical"/>
     <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
-    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
     <!-- Binding operating pb_type to physical pb_type -->
     <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
       <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->

openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml

@@ -139,15 +139,15 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
     <circuit_model type="lut" name="frac_lut4" prefix="frac_lut4" dump_structural_verilog="true">
       <design_technology type="cmos" fracturable_lut="true"/>
@@ -161,38 +161,37 @@
       <port type="output" prefix="lut3_out" size="2" lut_frac_level="3" lut_output_mask="0,1"/>
       <port type="output" prefix="lut4_out" size="1" lut_output_mask="0"/>
       <port type="sram" prefix="sram" size="16"/>
-      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
+      <port type="sram" prefix="mode" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="sram" name="config_latch" prefix="config_latch" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/config_latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/config_latch.v">
+    <circuit_model type="sram" name="LATCHR" prefix="LATCHR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/latch.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/latch.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
-       <port type="bl" prefix="bl" size="1"/>
-       <port type="wl" prefix="wl" size="1"/>
-       <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="bl" prefix="bl" lib_name="D" size="1"/>
+       <port type="wl" prefix="wl" lib_name="WE" size="1"/>
+       <port type="output" prefix="Q" lib_name="Q" size="1"/>
+       <port type="output" prefix="Qb" lib_name="QN" size="1"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
-    <circuit_model type="hard_logic" name="adder" prefix="adder" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
+    <circuit_model type="hard_logic" name="ADDF" prefix="ADDF" is_default="true" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/adder.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/adder.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="input" prefix="a" size="1"/>
-      <port type="input" prefix="b" size="1"/>
-      <port type="input" prefix="cin" size="1"/>
-      <port type="output" prefix="sumout" size="1"/>
-      <port type="output" prefix="cout" size="1"/>
+      <port type="input" prefix="a" lib_name="A" size="1"/>
+      <port type="input" prefix="b" lib_name="B" size="1"/>
+      <port type="input" prefix="cin" lib_name="CI" size="1"/>
+      <port type="output" prefix="sumout" lib_name="SUM" size="1"/>
+      <port type="output" prefix="cout" lib_name="CO" size="1"/>
     </circuit_model>
     <circuit_model type="hard_logic" name="dpram_128x8" prefix="dpram_128x8" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dpram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dpram1k.v">
       <design_technology type="cmos"/>
@@ -214,11 +213,11 @@
       <port type="input" prefix="b" size="32"/>
       <port type="output" prefix="out" size="64"/>
       <!-- As a fracturable multiplier, it requires 2 configuration bits to operate in 4 different modes -->
-      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="config_latch" default_val="1"/>
+      <port type="sram" prefix="mode" size="2" mode_select="true" circuit_model_name="LATCHR" default_val="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="frame_based" circuit_model_name="config_latch"/>
+    <organization type="frame_based" circuit_model_name="LATCHR"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
@@ -235,7 +234,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -248,8 +247,8 @@
     </pb_type>
     <pb_type name="clb.fle" physical_mode_name="physical"/>
     <pb_type name="clb.fle[physical].fabric.frac_logic.frac_lut4" circuit_model_name="frac_lut4" mode_bits="0"/>
-    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="static_dff"/>
-    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="adder"/>
+    <pb_type name="clb.fle[physical].fabric.ff" circuit_model_name="DFFSRQ"/>
+    <pb_type name="clb.fle[physical].fabric.adder" circuit_model_name="ADDF"/>
     <!-- Binding operating pb_type to physical pb_type -->
     <pb_type name="clb.fle[n2_lut3].lut3inter.ble3.lut3" physical_pb_type_name="clb.fle[physical].fabric.frac_logic.frac_lut4" mode_bits="1" physical_pb_type_index_factor="0.5">
       <!-- Binding the lut3 to the first 3 inputs of fracturable lut4 -->

openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml

@@ -124,15 +124,15 @@
       <port type="sram" prefix="sram" size="1"/>
     </circuit_model>
     <!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ff" name="static_dff" prefix="dff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
        <port type="input" prefix="D" size="1"/>
-       <port type="input" prefix="set" size="1" is_global="true" default_val="0" is_set="true"/>
-       <port type="input" prefix="reset" size="1" is_global="true" default_val="0" is_reset="true"/>
+       <port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
+       <port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
+       <port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
     </circuit_model>
     <circuit_model type="lut" name="lut6" prefix="lut6" dump_structural_verilog="true">
       <design_technology type="cmos"/>
@@ -146,28 +146,28 @@
       <port type="sram" prefix="sram" size="64"/>
     </circuit_model>
     <!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET>  -->
-    <circuit_model type="ccff" name="sc_dff_compact" prefix="scff" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/ff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/ff.v">
+    <circuit_model type="ccff" name="DFFR" prefix="DFFR" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/dff.v">
        <design_technology type="cmos"/>
        <input_buffer exist="true" circuit_model_name="INVTX1"/>
        <output_buffer exist="true" circuit_model_name="INVTX1"/>
-       <port type="input" prefix="pReset" lib_name="reset" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
+       <port type="input" prefix="pReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
        <port type="input" prefix="D" size="1"/>
        <port type="output" prefix="Q" size="1"/>
-       <port type="output" prefix="Qb" size="1"/>
-       <port type="clock" prefix="prog_clk" lib_name="clk" size="1" is_global="true" default_val="0" is_prog="true"/>
+       <port type="output" prefix="QN" size="1"/>
+       <port type="clock" prefix="prog_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true"/>
     </circuit_model>
-    <circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/io.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/io.v">
+    <circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/SpiceNetlists/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/VerilogNetlists/gpio.v">
       <design_technology type="cmos"/>
       <input_buffer exist="true" circuit_model_name="INVTX1"/>
       <output_buffer exist="true" circuit_model_name="INVTX1"/>
-      <port type="inout" prefix="pad" size="1" is_global="true" is_io="true"/>
-      <port type="sram" prefix="en" size="1" mode_select="true" circuit_model_name="sc_dff_compact" default_val="1"/>
-      <port type="input" prefix="outpad" size="1"/>
-      <port type="output" prefix="inpad" size="1"/>
+      <port type="inout" prefix="PAD" size="1" is_global="true" is_io="true"/>
+      <port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="DFFR" default_val="1"/>
+      <port type="input" prefix="outpad" lib_name="A" size="1"/>
+      <port type="output" prefix="inpad" lib_name="Y" size="1"/>
     </circuit_model>
   </circuit_library>
   <configuration_protocol>
-    <organization type="scan_chain" circuit_model_name="sc_dff_compact"/>
+    <organization type="scan_chain" circuit_model_name="DFFR"/>
   </configuration_protocol>
   <connection_block>
     <switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
@@ -181,7 +181,7 @@
   <pb_type_annotations>
     <!-- physical pb_type binding in complex block IO -->
     <pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
-    <pb_type name="io[physical].iopad" circuit_model_name="iopad" mode_bits="1"/> 
+    <pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/> 
     <pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/> 
     <pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/> 
     <!-- End physical pb_type binding in complex block IO -->
@@ -193,7 +193,7 @@
       <interconnect name="crossbar" circuit_model_name="mux_2level"/>
     </pb_type>
     <pb_type name="clb.fle[n1_lut6].ble6.lut6" circuit_model_name="lut6"/>
-    <pb_type name="clb.fle[n1_lut6].ble6.ff" circuit_model_name="static_dff"/>
+    <pb_type name="clb.fle[n1_lut6].ble6.ff" circuit_model_name="DFFSRQ"/>
     <!-- End physical pb_type binding in complex block IO -->
   </pb_type_annotations>
 </openfpga_architecture>