diff --git a/.travis/basic_reg_test.sh b/.travis/basic_reg_test.sh index 85cb514e4..f84af4b37 100755 --- a/.travis/basic_reg_test.sh +++ b/.travis/basic_reg_test.sh @@ -12,23 +12,49 @@ echo -e "Basic regression tests"; echo -e "Testing configuration chain of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_reset --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_resetb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_setb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_chain_use_set_reset --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_chain_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs echo -e "Testing fram-based configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_configuration_frame --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_configuration_frame_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_ccff --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_scff --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_reset --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_resetb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_setb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/configuration_frame_use_set_reset --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/configuration_frame --debug --show_thread_logs echo -e "Testing memory bank configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_reset --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_resetb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_setb --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/memory_bank_use_set_reset --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/fast_memory_bank_use_set --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/smart_fast_memory_bank --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/memory_bank --debug --show_thread_logs echo -e "Testing standalone (flatten memory) configuration protocol of a K4N4 FPGA"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/full_testbench/flatten_memory --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/preconfig_testbench/flatten_memory --debug --show_thread_logs +echo -e "Testing fixed device layout and routing channel width"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/fixed_device_support --debug --show_thread_logs + echo -e "Testing fabric Verilog generation only"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/generate_fabric --debug --show_thread_logs @@ -51,5 +77,7 @@ echo -e "Testing K4N4 with multiple lengths of routing segments"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_L124 --debug --show_thread_logs echo -e "Testing K4N4 with 32-bit fracturable multiplier"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n4_frac_mult --debug --show_thread_logs +echo -e "Testing K4N5 with pattern based local routing"; +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/k4_series/k4n5_pattern_local_routing --debug --show_thread_logs end_section "OpenFPGA.TaskTun" diff --git a/docs/source/manual/arch_lang/circuit_library.rst b/docs/source/manual/arch_lang/circuit_library.rst index 59e5f055f..9e8466c09 100644 --- a/docs/source/manual/arch_lang/circuit_library.rst +++ b/docs/source/manual/arch_lang/circuit_library.rst @@ -143,7 +143,8 @@ A circuit model may consist of a number of ports. The port list is mandatory in .. option:: + is_global="" is_set="" is_reset="" + is_edge_triggered="" is_config_enable=""/> Define the attributes for a port of a circuit model. @@ -190,6 +191,8 @@ A circuit model may consist of a number of ports. The port list is mandatory in - ``is_config_enable="true|false"`` Specify if this port controls a configuration-enable signal. Only valid when ``is_global`` is ``true``. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches. + - ``is_edge_triggered="true|false"`` Specify if this port is edge sensitive, like the clock port of a D-type flip-flop. This attribute is used to create stimuli in testbenches when flip-flops are used as configurable memory in frame-based configuration protocol. + .. note:: ``is_set``, ``is_reset`` and ``is_config_enable`` are only valid when ``is_global`` is ``true``. .. note:: Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of :ref:``circuit_model_example`` for more details. diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index c2044cf57..24dc3a603 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -33,6 +33,8 @@ write_verilog_testbench - ``--fast_configuration`` Enable fast configuration phase for the top-level testbench in order to reduce runtime of simulations. It is applicable to configuration chain, memory bank and frame-based configuration protocols. For configuration chain, when enabled, the zeros at the head of the bitstream will be skipped. For memory bank and frame-based, when enabled, all the zero configuration bits will be skipped. So ensure that your memory cells can be correctly reset to zero with a reset signal. + .. note:: If both reset and set ports are defined in the circuit modeling for programming, OpenFPGA will pick the one that will bring largest benefit in speeding up configuration. + - ``--print_top_testbench`` Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA - ``--print_formal_verification_top_netlist`` Generate a top-level module which can be used in formal verification diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.cpp b/libopenfpga/libarchopenfpga/src/circuit_library.cpp index bbf9c50c4..d8069f903 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/circuit_library.cpp @@ -942,6 +942,12 @@ bool CircuitLibrary::port_is_config_enable(const CircuitPortId& circuit_port_id) return port_is_config_enable_[circuit_port_id]; } +bool CircuitLibrary::port_is_edge_triggered(const CircuitPortId& circuit_port_id) const { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + return port_is_edge_triggered_[circuit_port_id]; +} + /* Return a flag if the port is used during programming a FPGA in a circuit model */ bool CircuitLibrary::port_is_prog(const CircuitPortId& circuit_port_id) const { /* validate the circuit_port_id */ @@ -1374,6 +1380,7 @@ CircuitPortId CircuitLibrary::add_model_port(const CircuitModelId& model_id, port_is_reset_.push_back(false); port_is_set_.push_back(false); port_is_config_enable_.push_back(false); + port_is_edge_triggered_.push_back(false); port_is_prog_.push_back(false); port_tri_state_model_names_.emplace_back(); port_tri_state_model_ids_.push_back(CircuitModelId::INVALID()); @@ -1493,6 +1500,15 @@ void CircuitLibrary::set_port_is_config_enable(const CircuitPortId& circuit_port return; } +/* Set the is_edge_triggered for a port of a circuit model */ +void CircuitLibrary::set_port_is_edge_triggered(const CircuitPortId& circuit_port_id, + const bool& is_edge_triggered) { + /* validate the circuit_port_id */ + VTR_ASSERT(valid_circuit_port_id(circuit_port_id)); + port_is_edge_triggered_[circuit_port_id] = is_edge_triggered; + return; +} + /* Set the is_prog for a port of a circuit model */ void CircuitLibrary::set_port_is_prog(const CircuitPortId& circuit_port_id, const bool& is_prog) { diff --git a/libopenfpga/libarchopenfpga/src/circuit_library.h b/libopenfpga/libarchopenfpga/src/circuit_library.h index bd082f738..f4b742a27 100644 --- a/libopenfpga/libarchopenfpga/src/circuit_library.h +++ b/libopenfpga/libarchopenfpga/src/circuit_library.h @@ -91,15 +91,16 @@ * 9. port_is_reset: specify if this port is a reset signal which needs special pulse widths in testbenches * 10. port_is_set: specify if this port is a set signal which needs special pulse widths in testbenches * 11. port_is_config_enable: specify if this port is a config_enable signal which needs special pulse widths in testbenches - * 12. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches - * 13. port_tri_state_model_name: the name of circuit model linked to tri-state the port - * 14. port_tri_state_model_ids_: the Id of circuit model linked to tri-state the port - * 15. port_inv_model_names_: the name of inverter circuit model linked to the port - * 16. port_inv_model_ids_: the Id of inverter circuit model linked to the port - * 17. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port - * 18. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used - * 19. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used - * 20. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains + * 12. port_is_edge_triggered: specify if this port is triggerd by edges like the clock signal of a D-type flip-flop + * 13. port_is_prog: specify if this port is for FPGA programming use which needs special pulse widths in testbenches + * 14. port_tri_state_model_name: the name of circuit model linked to tri-state the port + * 15. port_tri_state_model_ids_: the Id of circuit model linked to tri-state the port + * 16. port_inv_model_names_: the name of inverter circuit model linked to the port + * 17. port_inv_model_ids_: the Id of inverter circuit model linked to the port + * 18. port_tri_state_map_: only applicable to inputs of LUTs, the tri-state map applied to each pin of this port + * 19. port_lut_frac_level_: only applicable to outputs of LUTs, indicate which level of outputs inside LUT multiplexing structure will be used + * 20. port_lut_output_mask_: only applicable to outputs of LUTs, indicate which output at an internal level of LUT multiplexing structure will be used + * 21. port_sram_orgz_: only applicable to SRAM ports, indicate how the SRAMs will be organized, either memory decoders or scan-chains * * ------ Delay information ------ * 1. delay_types_: type of pin-to-pin delay, either rising_edge of falling_edge @@ -284,6 +285,7 @@ class CircuitLibrary { bool port_is_reset(const CircuitPortId& circuit_port_id) const; bool port_is_set(const CircuitPortId& circuit_port_id) const; bool port_is_config_enable(const CircuitPortId& circuit_port_id) const; + bool port_is_edge_triggered(const CircuitPortId& circuit_port_id) const; bool port_is_prog(const CircuitPortId& circuit_port_id) const; size_t port_lut_frac_level(const CircuitPortId& circuit_port_id) const; std::vector port_lut_output_mask(const CircuitPortId& circuit_port_id) const; @@ -364,6 +366,8 @@ class CircuitLibrary { const bool& is_set); void set_port_is_config_enable(const CircuitPortId& circuit_port_id, const bool& is_config_enable); + void set_port_is_edge_triggered(const CircuitPortId& circuit_port_id, + const bool& is_edge_triggered); void set_port_is_prog(const CircuitPortId& circuit_port_id, const bool& is_prog); void set_port_tri_state_model_name(const CircuitPortId& circuit_port_id, @@ -550,6 +554,7 @@ class CircuitLibrary { vtr::vector port_is_reset_; vtr::vector port_is_set_; vtr::vector port_is_config_enable_; + vtr::vector port_is_edge_triggered_; vtr::vector port_is_prog_; vtr::vector port_tri_state_model_names_; vtr::vector port_tri_state_model_ids_; diff --git a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp index 36e837814..4136b0463 100644 --- a/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/read_xml_circuit_library.cpp @@ -564,6 +564,9 @@ void read_xml_circuit_port(pugi::xml_node& xml_port, /* Identify if the port is to enable programming for FPGAs, by default it is NOT */ circuit_lib.set_port_is_config_enable(port, get_attribute(xml_port, "is_config_enable", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); + /* Identify if the port is to triggered by edges, by default it is NOT */ + circuit_lib.set_port_is_edge_triggered(port, get_attribute(xml_port, "is_edge_triggered", loc_data, pugiutil::ReqOpt::OPTIONAL).as_bool(false)); + /* Find the name of circuit model that this port is linked to */ circuit_lib.set_port_tri_state_model_name(port, get_attribute(xml_port, "circuit_model_name", loc_data, pugiutil::ReqOpt::OPTIONAL).as_string()); diff --git a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp index b141b0fe2..9165725e2 100644 --- a/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp +++ b/libopenfpga/libarchopenfpga/src/write_xml_circuit_library.cpp @@ -207,6 +207,10 @@ void write_xml_circuit_port(std::fstream& fp, write_xml_attribute(fp, "is_config_enable", "true"); } + if (true == circuit_lib.port_is_edge_triggered(port)) { + write_xml_attribute(fp, "is_edge_triggered", "true"); + } + /* Output the name of circuit model that this port is linked to */ if (!circuit_lib.port_tri_state_model_name(port).empty()) { write_xml_attribute(fp, "circuit_model_name", circuit_lib.port_tri_state_model_name(port).c_str()); diff --git a/openfpga/src/base/openfpga_verilog.cpp b/openfpga/src/base/openfpga_verilog.cpp index 58ea20f2e..0c6367fc5 100644 --- a/openfpga/src/base/openfpga_verilog.cpp +++ b/openfpga/src/base/openfpga_verilog.cpp @@ -97,7 +97,7 @@ int write_verilog_testbench(OpenfpgaContext& openfpga_ctx, openfpga_ctx.vpr_netlist_annotation(), openfpga_ctx.arch().circuit_lib, openfpga_ctx.simulation_setting(), - openfpga_ctx.arch().config_protocol.type(), + openfpga_ctx.arch().config_protocol, options); /* TODO: should identify the error code from internal function execution */ diff --git a/openfpga/src/fabric/build_memory_modules.cpp b/openfpga/src/fabric/build_memory_modules.cpp index b9b83508a..32d1c93b2 100644 --- a/openfpga/src/fabric/build_memory_modules.cpp +++ b/openfpga/src/fabric/build_memory_modules.cpp @@ -636,13 +636,13 @@ void build_frame_memory_module(ModuleManager& module_manager, module_manager.add_configurable_child(mem_module, sram_mem_module, sram_instance); /* Wire data_in port to SRAM BL port */ - ModulePortId sram_bl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_lib_name(sram_bl_ports[0])); + ModulePortId sram_bl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_prefix(sram_bl_ports[0])); add_module_bus_nets(module_manager, mem_module, mem_module, 0, mem_data_port, sram_mem_module, sram_instance, sram_bl_port); /* Wire decoder data_out port to sram WL ports */ - ModulePortId sram_wl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_lib_name(sram_wl_ports[0])); + ModulePortId sram_wl_port = module_manager.find_module_port(sram_mem_module, circuit_lib.port_prefix(sram_wl_ports[0])); ModulePortId decoder_data_port = module_manager.find_module_port(decoder_module, std::string(DECODER_DATA_OUT_PORT_NAME)); ModuleNetId wl_net = module_manager.create_module_net(mem_module); /* Source node of the input net is the input of memory module */ diff --git a/openfpga/src/fpga_verilog/verilog_api.cpp b/openfpga/src/fpga_verilog/verilog_api.cpp index 940d78953..fe5b76196 100644 --- a/openfpga/src/fpga_verilog/verilog_api.cpp +++ b/openfpga/src/fpga_verilog/verilog_api.cpp @@ -156,7 +156,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager, const VprNetlistAnnotation &netlist_annotation, const CircuitLibrary &circuit_lib, const SimulationSetting &simulation_setting, - const e_config_protocol_type &config_protocol_type, + const ConfigProtocol &config_protocol, const VerilogTestbenchOption &options) { vtr::ScopedStartFinishTimer timer("Write Verilog testbenches for FPGA fabric\n"); @@ -205,7 +205,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager, std::string top_testbench_file_path = src_dir_path + netlist_name + std::string(AUTOCHECK_TOP_TESTBENCH_VERILOG_FILE_POSTFIX); print_verilog_top_testbench(module_manager, bitstream_manager, fabric_bitstream, - config_protocol_type, + config_protocol, circuit_lib, global_ports, atom_ctx, place_ctx, io_location_map, netlist_annotation, @@ -225,7 +225,7 @@ void fpga_verilog_testbench(const ModuleManager &module_manager, src_dir_path, atom_ctx, place_ctx, io_location_map, module_manager, - config_protocol_type, + config_protocol.type(), bitstream_manager.num_bits(), simulation_setting.num_clock_cycles(), simulation_setting.programming_clock_frequency(), diff --git a/openfpga/src/fpga_verilog/verilog_api.h b/openfpga/src/fpga_verilog/verilog_api.h index 94fbf3a29..1af656d7d 100644 --- a/openfpga/src/fpga_verilog/verilog_api.h +++ b/openfpga/src/fpga_verilog/verilog_api.h @@ -10,6 +10,7 @@ #include "mux_library.h" #include "decoder_library.h" #include "circuit_library.h" +#include "config_protocol.h" #include "vpr_context.h" #include "vpr_device_annotation.h" #include "device_rr_gsb.h" @@ -49,7 +50,7 @@ void fpga_verilog_testbench(const ModuleManager& module_manager, const VprNetlistAnnotation& netlist_annotation, const CircuitLibrary& circuit_lib, const SimulationSetting& simulation_parameters, - const e_config_protocol_type& config_protocol_type, + const ConfigProtocol& config_protocol, const VerilogTestbenchOption& options); diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp index 27f714957..c4250bdcc 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.cpp +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.cpp @@ -60,6 +60,54 @@ constexpr char* TOP_TB_CLOCK_REG_POSTFIX = "_reg"; constexpr char* AUTOCHECK_TOP_TESTBENCH_VERILOG_MODULE_POSTFIX = "_autocheck_top_tb"; +/******************************************************************** + * Identify global reset ports for programming + *******************************************************************/ +static +std::vector find_global_programming_reset_ports(const CircuitLibrary& circuit_lib, + const std::vector& global_ports) { + /* Try to find global reset ports for programming */ + std::vector global_prog_reset_ports; + for (const CircuitPortId& global_port : global_ports) { + VTR_ASSERT(true == circuit_lib.port_is_global(global_port)); + if (false == circuit_lib.port_is_prog(global_port)) { + continue; + } + VTR_ASSERT(true == circuit_lib.port_is_prog(global_port)); + VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port)) + || (false == circuit_lib.port_is_set(global_port))); + if (true == circuit_lib.port_is_reset(global_port)) { + global_prog_reset_ports.push_back(global_port); + } + } + + return global_prog_reset_ports; +} + +/******************************************************************** + * Identify global set ports for programming + *******************************************************************/ +static +std::vector find_global_programming_set_ports(const CircuitLibrary& circuit_lib, + const std::vector& global_ports) { + /* Try to find global set ports for programming */ + std::vector global_prog_set_ports; + for (const CircuitPortId& global_port : global_ports) { + VTR_ASSERT(true == circuit_lib.port_is_global(global_port)); + if (false == circuit_lib.port_is_prog(global_port)) { + continue; + } + VTR_ASSERT(true == circuit_lib.port_is_prog(global_port)); + VTR_ASSERT( (false == circuit_lib.port_is_reset(global_port)) + || (false == circuit_lib.port_is_set(global_port))); + if (true == circuit_lib.port_is_set(global_port)) { + global_prog_set_ports.push_back(global_port); + } + } + + return global_prog_set_ports; +} + /******************************************************************** * Print local wires for flatten memory (standalone) configuration protocols *******************************************************************/ @@ -136,15 +184,15 @@ void print_verilog_top_testbench_memory_bank_port(std::fstream& fp, BasicPort din_port = module_manager.module_port(top_module, din_port_id); fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl; - /* Wire the INVERTED programming clock to the enable signal !!! */ - print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock -----")); + /* Wire the INVERTED configuration done signal to the enable signal !!! */ + print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----")); ModulePortId en_port_id = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME)); BasicPort en_port = module_manager.module_port(top_module, en_port_id); - BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); + BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; - print_verilog_wire_connection(fp, en_port, prog_clock_port, true); + print_verilog_wire_connection(fp, en_port, config_done_port, true); } @@ -153,6 +201,8 @@ void print_verilog_top_testbench_memory_bank_port(std::fstream& fp, *******************************************************************/ static void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, + const ConfigProtocol& config_protocol, + const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, const ModuleId& top_module) { /* Validate the file stream */ @@ -173,15 +223,33 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, BasicPort din_port = module_manager.module_port(top_module, din_port_id); fp << generate_verilog_port(VERILOG_PORT_REG, din_port) << ";" << std::endl; - /* Wire the INVERTED programming clock to the enable signal !!! */ - print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock -----")); + /* Wire the INVERTED configuration done signal to the enable signal !!! */ ModulePortId en_port_id = module_manager.find_module_port(top_module, std::string(DECODER_ENABLE_PORT_NAME)); BasicPort en_port = module_manager.module_port(top_module, en_port_id); - BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); - fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; - print_verilog_wire_connection(fp, en_port, prog_clock_port, true); + /* Find the circuit model of configurable memory + * Spot its BL port and generate stimuli based on BL port's attribute: + * - If the BL port is triggered by edge, use the inverted programming clock signal + * - If the BL port is a regular port, use the inverted configuration done signal + */ + const CircuitModelId& mem_model = config_protocol.memory_model(); + VTR_ASSERT(true == circuit_lib.valid_model_id(mem_model)); + std::vector mem_model_bl_ports = circuit_lib.model_ports_by_type(mem_model, CIRCUIT_MODEL_PORT_BL); + VTR_ASSERT(1 == mem_model_bl_ports.size()); + + if (true == circuit_lib.port_is_edge_triggered(mem_model_bl_ports[0])) { + VTR_ASSERT_SAFE(false == circuit_lib.port_is_edge_triggered(mem_model_bl_ports[0])); + BasicPort prog_clock_port(std::string(TOP_TB_PROG_CLOCK_PORT_NAME), 1); + print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted programming clock signal -----")); + fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; + print_verilog_wire_connection(fp, en_port, prog_clock_port, true); + } else { + BasicPort config_done_port(std::string(TOP_TB_CONFIG_DONE_PORT_NAME), 1); + print_verilog_comment(fp, std::string("---- Wire enable port of frame-based decoder to inverted configuration done signal -----")); + fp << generate_verilog_port(VERILOG_PORT_WIRE, en_port) << ";" << std::endl; + print_verilog_wire_connection(fp, en_port, config_done_port, true); + } } /******************************************************************** @@ -189,10 +257,11 @@ void print_verilog_top_testbench_frame_decoder_port(std::fstream& fp, *******************************************************************/ static void print_verilog_top_testbench_config_protocol_port(std::fstream& fp, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, + const CircuitLibrary& circuit_lib, const ModuleManager& module_manager, const ModuleId& top_module) { - switch(sram_orgz_type) { + switch(config_protocol.type()) { case CONFIG_MEM_STANDALONE: print_verilog_top_testbench_flatten_memory_port(fp, module_manager, top_module); break; @@ -203,7 +272,8 @@ void print_verilog_top_testbench_config_protocol_port(std::fstream& fp, print_verilog_top_testbench_memory_bank_port(fp, module_manager, top_module); break; case CONFIG_MEM_FRAME_BASED: - print_verilog_top_testbench_frame_decoder_port(fp, module_manager, top_module); + print_verilog_top_testbench_frame_decoder_port(fp, config_protocol, circuit_lib, + module_manager, top_module); break; default: VTR_LOGF_ERROR(__FILE__, __LINE__, @@ -220,7 +290,9 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, const ModuleManager& module_manager, const ModuleId& top_module, const CircuitLibrary& circuit_lib, - const std::vector& global_ports) { + const std::vector& global_ports, + const bool& active_global_prog_reset, + const bool& active_global_prog_set) { /* Validate the file stream */ valid_file_stream(fp); @@ -302,10 +374,13 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port)); VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); + /* For global programming reset port, we will active only when specified */ BasicPort stimuli_reset_port; + bool activate = true; if (true == circuit_lib.port_is_prog(model_global_port)) { stimuli_reset_port.set_name(std::string(TOP_TB_PROG_RESET_PORT_NAME)); stimuli_reset_port.set_width(1); + activate = active_global_prog_reset; } else { VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port)); stimuli_reset_port.set_name(std::string(TOP_TB_RESET_PORT_NAME)); @@ -315,9 +390,15 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, * The wiring will be inverted if the default value of the global port is 1 * Otherwise, the wiring will not be inverted! */ - print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), - stimuli_reset_port, - 1 == circuit_lib.port_default_value(model_global_port)); + if (true == activate) { + print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), + stimuli_reset_port, + 1 == circuit_lib.port_default_value(model_global_port)); + } else { + VTR_ASSERT_SAFE(false == activate); + print_verilog_wire_constant_values(fp, module_manager.module_port(top_module, module_global_port), + std::vector(1, circuit_lib.port_default_value(model_global_port))); + } } /* Connect global set ports to operating or programming set signal */ @@ -344,10 +425,13 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, ModulePortId module_global_port = module_manager.find_module_port(top_module, circuit_lib.port_prefix(model_global_port)); VTR_ASSERT(true == module_manager.valid_module_port_id(top_module, module_global_port)); + /* For global programming set port, we will active only when specified */ BasicPort stimuli_set_port; + bool activate = true; if (true == circuit_lib.port_is_prog(model_global_port)) { stimuli_set_port.set_name(std::string(TOP_TB_PROG_SET_PORT_NAME)); stimuli_set_port.set_width(1); + activate = active_global_prog_set; } else { VTR_ASSERT_SAFE(false == circuit_lib.port_is_prog(model_global_port)); stimuli_set_port.set_name(std::string(TOP_TB_SET_PORT_NAME)); @@ -357,9 +441,15 @@ void print_verilog_top_testbench_global_ports_stimuli(std::fstream& fp, * The wiring will be inverted if the default value of the global port is 1 * Otherwise, the wiring will not be inverted! */ - print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), - stimuli_set_port, - 1 == circuit_lib.port_default_value(model_global_port)); + if (true == activate) { + print_verilog_wire_connection(fp, module_manager.module_port(top_module, module_global_port), + stimuli_set_port, + 1 == circuit_lib.port_default_value(model_global_port)); + } else { + VTR_ASSERT_SAFE(false == activate); + print_verilog_wire_constant_values(fp, module_manager.module_port(top_module, module_global_port), + std::vector(1, circuit_lib.port_default_value(model_global_port))); + } } /* For the rest of global ports, wire them to constant signals */ @@ -434,7 +524,8 @@ void print_verilog_top_testbench_ports(std::fstream& fp, const AtomContext& atom_ctx, const VprNetlistAnnotation& netlist_annotation, const std::vector& clock_port_names, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, + const CircuitLibrary& circuit_lib, const std::string& circuit_name){ /* Validate the file stream */ valid_file_stream(fp); @@ -508,7 +599,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp, fp << generate_verilog_port(VERILOG_PORT_REG, set_port) << ";" << std::endl; /* Configuration ports depend on the organization of SRAMs */ - print_verilog_top_testbench_config_protocol_port(fp, sram_orgz_type, + print_verilog_top_testbench_config_protocol_port(fp, config_protocol, circuit_lib, module_manager, top_module); /* Create a clock port if the benchmark have one but not in the default name! @@ -561,6 +652,7 @@ void print_verilog_top_testbench_ports(std::fstream& fp, static size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz_type, const bool& fast_configuration, + const bool& bit_value_to_skip, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream) { size_t num_config_clock_cycles = 1 + fabric_bitstream.num_bits(); @@ -579,7 +671,7 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz size_t full_num_config_clock_cycles = num_config_clock_cycles; size_t num_bits_to_skip = 0; for (const FabricBitId& bit_id : fabric_bitstream.bits()) { - if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { + if (bit_value_to_skip != bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { break; } num_bits_to_skip++; @@ -600,7 +692,7 @@ size_t calculate_num_config_clock_cycles(const e_config_protocol_type& sram_orgz size_t full_num_config_clock_cycles = num_config_clock_cycles; num_config_clock_cycles = 1; for (const FabricBitId& bit_id : fabric_bitstream.bits()) { - if (true == fabric_bitstream.bit_din(bit_id)) { + if (bit_value_to_skip != fabric_bitstream.bit_din(bit_id)) { num_config_clock_cycles++; } } @@ -985,11 +1077,11 @@ void print_verilog_top_testbench_generic_stimulus(std::fstream& fp, fp << std::endl; /* Programming set signal for configuration circuit : always disabled */ - print_verilog_comment(fp, "----- Begin programming set signal generation: always disabled -----"); + print_verilog_comment(fp, "----- Begin programming set signal generation -----"); print_verilog_pulse_stimuli(fp, prog_set_port, - 0, /* Initial value */ + 1, /* Initial value */ prog_clock_period / timescale, 0); - print_verilog_comment(fp, "----- End programming set signal generation: always disabled -----"); + print_verilog_comment(fp, "----- End programming set signal generation -----"); fp << std::endl; @@ -1112,6 +1204,102 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp, print_verilog_comment(fp, "----- End bitstream loading during configuration phase -----"); } +/******************************************************************** + * Decide if we should use reset or set signal to acheive fast configuration + * - If only one type signal is specified, we use that type + * For example, only reset signal is defined, we will use reset + * - If both are defined, pick the one that will bring bigger reduction + * i.e., larger number of configuration bits can be skipped + *******************************************************************/ +static +bool find_bit_value_to_skip_for_fast_configuration(const e_config_protocol_type& config_protocol_type, + const bool& fast_configuration, + const std::vector& global_prog_reset_ports, + const std::vector& global_prog_set_ports, + const BitstreamManager& bitstream_manager, + const FabricBitstream& fabric_bitstream) { + + /* Early exit conditions */ + if (!global_prog_reset_ports.empty() && global_prog_set_ports.empty()) { + return false; + } else if (!global_prog_set_ports.empty() && global_prog_reset_ports.empty()) { + return true; + } else if (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) { + /* If both types of ports are not defined, the fast configuration should be turned off */ + VTR_ASSERT(false == fast_configuration); + return false; + } + + VTR_ASSERT(!global_prog_set_ports.empty() && !global_prog_reset_ports.empty()); + bool bit_value_to_skip = false; + + VTR_LOG("Both reset and set ports are defined for programming controls, selecting the best-fit one...\n"); + + size_t num_ones_to_skip = 0; + size_t num_zeros_to_skip = 0; + + /* Branch on the type of configuration protocol */ + switch (config_protocol_type) { + case CONFIG_MEM_STANDALONE: + break; + case CONFIG_MEM_SCAN_CHAIN: { + /* We can only skip the ones/zeros at the beginning of the bitstream */ + /* Count how many logic '1' bits we can skip */ + for (const FabricBitId& bit_id : fabric_bitstream.bits()) { + if (false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { + break; + } + VTR_ASSERT(true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))); + num_ones_to_skip++; + } + /* Count how many logic '0' bits we can skip */ + for (const FabricBitId& bit_id : fabric_bitstream.bits()) { + if (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { + break; + } + VTR_ASSERT(false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))); + num_zeros_to_skip++; + } + break; + } + case CONFIG_MEM_MEMORY_BANK: + case CONFIG_MEM_FRAME_BASED: { + /* Count how many logic '1' and logic '0' bits we can skip */ + for (const FabricBitId& bit_id : fabric_bitstream.bits()) { + if (false == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))) { + num_zeros_to_skip++; + } else { + VTR_ASSERT(true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id))); + num_ones_to_skip++; + } + } + break; + } + default: + VTR_LOGF_ERROR(__FILE__, __LINE__, + "Invalid SRAM organization type!\n"); + exit(1); + } + + VTR_LOG("Using reset will skip %g% (%lu/%lu) of configuration bitstream.\n", + 100. * (float) num_zeros_to_skip / (float) fabric_bitstream.num_bits(), + num_zeros_to_skip, fabric_bitstream.num_bits()); + + VTR_LOG("Using set will skip %g% (%lu/%lu) of configuration bitstream.\n", + 100. * (float) num_ones_to_skip / (float) fabric_bitstream.num_bits(), + num_ones_to_skip, fabric_bitstream.num_bits()); + + /* By default, we prefer to skip zeros (when the numbers are the same */ + if (num_ones_to_skip > num_zeros_to_skip) { + VTR_LOG("Will use set signal in fast configuration\n"); + bit_value_to_skip = true; + } else { + VTR_LOG("Will use reset signal in fast configuration\n"); + } + + return bit_value_to_skip; +} + /******************************************************************** * Print stimulus for a FPGA fabric with a configuration chain protocol * where configuration bits are programming in serial (one by one) @@ -1127,6 +1315,7 @@ void print_verilog_top_testbench_vanilla_bitstream(std::fstream& fp, static void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, const bool& fast_configuration, + const bool& bit_value_to_skip, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream) { /* Validate the file stream */ @@ -1151,13 +1340,14 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, fp << std::endl; + /* Attention: when the fast configuration is enabled, we will start from the first bit '1' * This requires a reset signal (as we forced in the first clock cycle) */ bool start_config = false; for (const FabricBitId& bit_id : fabric_bitstream.bits()) { if ( (false == start_config) - && (true == bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)))) { + && (bit_value_to_skip != bitstream_manager.bit_value(fabric_bitstream.config_bit(bit_id)))) { start_config = true; } @@ -1198,6 +1388,7 @@ void print_verilog_top_testbench_configuration_chain_bitstream(std::fstream& fp, static void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp, const bool& fast_configuration, + const bool& bit_value_to_skip, const ModuleManager& module_manager, const ModuleId& top_module, const FabricBitstream& fabric_bitstream) { @@ -1249,7 +1440,7 @@ void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp, for (const FabricBitId& bit_id : fabric_bitstream.bits()) { /* When fast configuration is enabled, we skip zero data_in values */ if ((true == fast_configuration) - && (false == fabric_bitstream.bit_din(bit_id))) { + && (bit_value_to_skip == fabric_bitstream.bit_din(bit_id))) { continue; } @@ -1303,6 +1494,7 @@ void print_verilog_top_testbench_memory_bank_bitstream(std::fstream& fp, static void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp, const bool& fast_configuration, + const bool& bit_value_to_skip, const ModuleManager& module_manager, const ModuleId& top_module, const FabricBitstream& fabric_bitstream) { @@ -1345,7 +1537,7 @@ void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp, for (const FabricBitId& bit_id : fabric_bitstream.bits()) { /* When fast configuration is enabled, we skip zero data_in values */ if ((true == fast_configuration) - && (false == fabric_bitstream.bit_din(bit_id))) { + && (bit_value_to_skip == fabric_bitstream.bit_din(bit_id))) { continue; } @@ -1401,14 +1593,16 @@ void print_verilog_top_testbench_frame_decoder_bitstream(std::fstream& fp, *******************************************************************/ static void print_verilog_top_testbench_bitstream(std::fstream& fp, - const e_config_protocol_type& sram_orgz_type, + const e_config_protocol_type& config_protocol_type, const bool& fast_configuration, + const bool& bit_value_to_skip, const ModuleManager& module_manager, const ModuleId& top_module, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream) { + /* Branch on the type of configuration protocol */ - switch (sram_orgz_type) { + switch (config_protocol_type) { case CONFIG_MEM_STANDALONE: print_verilog_top_testbench_vanilla_bitstream(fp, module_manager, top_module, @@ -1416,15 +1610,18 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp, break; case CONFIG_MEM_SCAN_CHAIN: print_verilog_top_testbench_configuration_chain_bitstream(fp, fast_configuration, + bit_value_to_skip, bitstream_manager, fabric_bitstream); break; case CONFIG_MEM_MEMORY_BANK: print_verilog_top_testbench_memory_bank_bitstream(fp, fast_configuration, + bit_value_to_skip, module_manager, top_module, fabric_bitstream); break; case CONFIG_MEM_FRAME_BASED: print_verilog_top_testbench_frame_decoder_bitstream(fp, fast_configuration, + bit_value_to_skip, module_manager, top_module, fabric_bitstream); break; @@ -1458,7 +1655,7 @@ void print_verilog_top_testbench_bitstream(std::fstream& fp, void print_verilog_top_testbench(const ModuleManager& module_manager, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, const CircuitLibrary& circuit_lib, const std::vector& global_ports, const AtomContext& atom_ctx, @@ -1494,17 +1691,36 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* Preparation: find all the clock ports */ std::vector clock_port_names = find_atom_netlist_clock_port_names(atom_ctx.nlist, netlist_annotation); + /* Preparation: find all the reset/set ports for programming usage */ + std::vector global_prog_reset_ports = find_global_programming_reset_ports(circuit_lib, global_ports); + std::vector global_prog_set_ports = find_global_programming_set_ports(circuit_lib, global_ports); + + /* Identify if we can apply fast configuration */ + bool apply_fast_configuration = fast_configuration; + if ( (global_prog_set_ports.empty() && global_prog_reset_ports.empty()) + && (true == fast_configuration)) { + VTR_LOG_WARN("None of global reset and set ports are defined for programming purpose. Fast configuration is turned off\n"); + apply_fast_configuration = false; + } + bool bit_value_to_skip = find_bit_value_to_skip_for_fast_configuration(config_protocol.type(), + apply_fast_configuration, + global_prog_reset_ports, + global_prog_set_ports, + bitstream_manager, fabric_bitstream); + /* Start of testbench */ print_verilog_top_testbench_ports(fp, module_manager, top_module, atom_ctx, netlist_annotation, clock_port_names, - sram_orgz_type, circuit_name); + config_protocol, circuit_lib, + circuit_name); /* Find the clock period */ float prog_clock_period = (1./simulation_parameters.programming_clock_frequency()); float op_clock_period = (1./simulation_parameters.operating_clock_frequency()); /* Estimate the number of configuration clock cycles */ - size_t num_config_clock_cycles = calculate_num_config_clock_cycles(sram_orgz_type, - fast_configuration, + size_t num_config_clock_cycles = calculate_num_config_clock_cycles(config_protocol.type(), + apply_fast_configuration, + bit_value_to_skip, bitstream_manager, fabric_bitstream); @@ -1515,10 +1731,38 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, op_clock_period, VERILOG_SIM_TIMESCALE); + /* Identify the stimulus for global reset/set for programming purpose: + * - If only reset port is seen we turn on Reset + * - If only set port is seen we turn on Reset + * - If both reset and set port is defined, + * we pick the one which is consistent with the bit value to be skipped + */ + bool active_global_prog_reset = false; + bool active_global_prog_set = false; + + if (!global_prog_reset_ports.empty()) { + active_global_prog_reset = true; + } + + if (!global_prog_set_ports.empty()) { + active_global_prog_set = true; + } + + /* Ensure that at most only one of the two switches is activated */ + if ( (true == active_global_prog_reset) + && (true == active_global_prog_set) ) { + /* If we will skip logic '0', we will activate programming reset */ + active_global_prog_reset = !bit_value_to_skip; + /* If we will skip logic '1', we will activate programming set */ + active_global_prog_set = bit_value_to_skip; + } + /* Generate stimuli for global ports or connect them to existed signals */ print_verilog_top_testbench_global_ports_stimuli(fp, module_manager, top_module, - circuit_lib, global_ports); + circuit_lib, global_ports, + active_global_prog_reset, + active_global_prog_set); /* Instanciate FPGA top-level module */ print_verilog_testbench_fpga_instance(fp, module_manager, top_module, @@ -1542,12 +1786,13 @@ void print_verilog_top_testbench(const ModuleManager& module_manager, /* Print tasks used for loading bitstreams */ print_verilog_top_testbench_load_bitstream_task(fp, - sram_orgz_type, + config_protocol.type(), module_manager, top_module); /* load bitstream to FPGA fabric in a configuration phase */ - print_verilog_top_testbench_bitstream(fp, sram_orgz_type, - fast_configuration, + print_verilog_top_testbench_bitstream(fp, config_protocol.type(), + apply_fast_configuration, + bit_value_to_skip, module_manager, top_module, bitstream_manager, fabric_bitstream); diff --git a/openfpga/src/fpga_verilog/verilog_top_testbench.h b/openfpga/src/fpga_verilog/verilog_top_testbench.h index cbafc6dc4..64d0e0b26 100644 --- a/openfpga/src/fpga_verilog/verilog_top_testbench.h +++ b/openfpga/src/fpga_verilog/verilog_top_testbench.h @@ -10,6 +10,7 @@ #include "bitstream_manager.h" #include "fabric_bitstream.h" #include "circuit_library.h" +#include "config_protocol.h" #include "vpr_context.h" #include "io_location_map.h" #include "vpr_netlist_annotation.h" @@ -25,7 +26,7 @@ namespace openfpga { void print_verilog_top_testbench(const ModuleManager& module_manager, const BitstreamManager& bitstream_manager, const FabricBitstream& fabric_bitstream, - const e_config_protocol_type& sram_orgz_type, + const ConfigProtocol& config_protocol, const CircuitLibrary& circuit_lib, const std::vector& global_ports, const AtomContext& atom_ctx, diff --git a/openfpga/test_blif/and.act b/openfpga/test_blif/and.act deleted file mode 100644 index 0f77bc6b3..000000000 --- a/openfpga/test_blif/and.act +++ /dev/null @@ -1,3 +0,0 @@ -a 0.5 0.5 -b 0.5 0.5 -c 0.25 0.25 diff --git a/openfpga/test_blif/and.blif b/openfpga/test_blif/and.blif deleted file mode 100644 index 67d978741..000000000 --- a/openfpga/test_blif/and.blif +++ /dev/null @@ -1,8 +0,0 @@ -.model top -.inputs a b -.outputs c - -.names a b c -11 1 - -.end diff --git a/openfpga/test_blif/and.v b/openfpga/test_blif/and.v deleted file mode 100644 index 876f1c6fe..000000000 --- a/openfpga/test_blif/and.v +++ /dev/null @@ -1,14 +0,0 @@ -`timescale 1ns / 1ps - -module top( - a, - b, - c); - -input wire a; -input wire b; -output wire c; - -assign c = a & b; - -endmodule diff --git a/openfpga/test_blif/and_latch.act b/openfpga/test_blif/and_latch.act deleted file mode 100644 index 61bbe1fe8..000000000 --- a/openfpga/test_blif/and_latch.act +++ /dev/null @@ -1,6 +0,0 @@ -a 0.492800 0.201000 -b 0.502000 0.197200 -clk 0.500000 2.000000 -d 0.240200 0.171200 -c 0.240200 0.044100 -n1 0.240200 0.044100 diff --git a/openfpga/test_blif/and_latch.blif b/openfpga/test_blif/and_latch.blif deleted file mode 100644 index dbd863d9c..000000000 --- a/openfpga/test_blif/and_latch.blif +++ /dev/null @@ -1,14 +0,0 @@ -# Benchmark "top" written by ABC on Wed Mar 11 10:36:28 2020 -.model top -.inputs a b clk -.outputs c d - -.latch n1 d re clk 0 - -.names a b c -11 1 - -.names c n1 -1 1 - -.end diff --git a/openfpga/test_blif/and_latch.v b/openfpga/test_blif/and_latch.v deleted file mode 100644 index 893cdf7a4..000000000 --- a/openfpga/test_blif/and_latch.v +++ /dev/null @@ -1,23 +0,0 @@ -`timescale 1ns / 1ps - -module top( - clk, - a, - b, - c, - d); - -input wire clk; - -input wire a; -input wire b; -output wire c; -output reg d; - -assign c = a & b; - -always @(posedge clk) begin - d <= c; -end - -endmodule diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml deleted file mode 100644 index ae08c8250..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ /dev/null @@ -1,285 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml deleted file mode 100644 index cb145e06d..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ /dev/null @@ -1,302 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml deleted file mode 100644 index e65851291..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ /dev/null @@ -1,314 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml deleted file mode 100644 index 779880dea..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ /dev/null @@ -1,288 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml deleted file mode 100644 index 621847439..000000000 --- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ /dev/null @@ -1,294 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - 10e-12 - - - 10e-12 - - - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - - - - - - - - - - 10e-12 5e-12 5e-12 - - - 10e-12 5e-12 5e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_script/and_k6_frac.openfpga b/openfpga/test_script/and_k6_frac.openfpga deleted file mode 100644 index 90f20b2b7..000000000 --- a/openfpga/test_script/and_k6_frac.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges --verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -write_fabric_hierarchy --file ./fabric_hierarchy.txt - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/and.bitstream - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --hierarchical --file /var/tmp/xtang/openfpga_test_src/SDC_hie -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_adder_chain.openfpga deleted file mode 100644 index 3cdebb2b1..000000000 --- a/openfpga/test_script/and_k6_frac_adder_chain.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga deleted file mode 100644 index 34ec11181..000000000 --- a/openfpga/test_script/and_k6_frac_adder_chain_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable.openfpga b/openfpga/test_script/and_k6_frac_tileable.openfpga deleted file mode 100644 index 0731e6543..000000000 --- a/openfpga/test_script/and_k6_frac_tileable.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga deleted file mode 100644 index 05ea64bce..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain.openfpga +++ /dev/null @@ -1,64 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist - write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC \ - --explicit_port_mapping --include_timing --include_signal_init \ - --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga deleted file mode 100644 index ed0d8cc5a..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga deleted file mode 100644 index 492c70ea6..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_aib.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga deleted file mode 100644 index 29830f1db..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_multi_io_capacity.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga deleted file mode 100644 index 22a658a73..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_mem16K_reduced_io.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga deleted file mode 100644 index 466c3bcd0..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_chain_wide_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga b/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga deleted file mode 100644 index 864fea78d..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_adder_register_scan_chain.openfpga +++ /dev/null @@ -1,63 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc \ - --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_spyio.openfpga b/openfpga/test_script/and_k6_frac_tileable_spyio.openfpga deleted file mode 100644 index 7b9fa407c..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_spyio.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga b/openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga deleted file mode 100644 index 04ff99d8c..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_stdcell_mux2.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga b/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga deleted file mode 100644 index 5b1177586..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_thru_channel_adder_chain_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga b/openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga deleted file mode 100644 index 95cd2a3c3..000000000 --- a/openfpga/test_script/and_k6_frac_tileable_tree_mux.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_latch_k6_frac.openfpga b/openfpga/test_script/and_latch_k6_frac.openfpga deleted file mode 100644 index b41ac4450..000000000 --- a/openfpga/test_script/and_latch_k6_frac.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and_latch' design -vpr ./test_vpr_arch/k6_frac_N10_40nm.xml ./test_blif/and_latch.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack --verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_latch_k6_frac_tileable.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable.openfpga deleted file mode 100644 index c89174d2d..000000000 --- a/openfpga/test_script/and_latch_k6_frac_tileable.openfpga +++ /dev/null @@ -1,59 +0,0 @@ -# Run VPR for the 'and_latch' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_40nm.xml ./test_blif/and_latch.blif --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin #--verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack --verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga deleted file mode 100644 index ef49426d0..000000000 --- a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and_latch.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga b/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga deleted file mode 100644 index 87c69c880..000000000 --- a/openfpga/test_script/and_latch_k6_frac_tileable_adder_chain_mem16K.openfpga +++ /dev/null @@ -1,62 +0,0 @@ -# Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml ./test_blif/and_latch.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml - -# Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml - -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml - -# Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and_latch.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml - -# Check and correct any naming conflicts in the BLIF netlist -check_netlist_naming_conflict --fix --report ./netlist_renaming.xml - -# Apply fix-up to clustering nets based on routing results -pb_pin_fixup --verbose - -# Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose - -# Build the module graph -# - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose - -# Repack the netlist to physical pbs -# This must be done before bitstream generator and testbench generation -# Strongly recommend it is done after all the fix-up have been applied -repack #--verbose - -# Build the bitstream -# - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml - -# Build fabric-dependent bitstream -build_fabric_bitstream --verbose - -# Write the Verilog netlist for FPGA fabric -# - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose - -# Write the Verilog testbench for FPGA fabric -# - We suggest the use of same output directory as fabric Verilog netlists -# - Must specify the reference benchmark file if you want to output any testbenches -# - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA -# - Enable pre-configured top-level testbench which is a fast verification skipping programming phase -# - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and_latch.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini - -# Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC - -# Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis - -# Finish and exit OpenFPGA -exit diff --git a/openfpga/test_vpr_arch/k6_N10_40nm.xml b/openfpga/test_vpr_arch/k6_N10_40nm.xml deleted file mode 100644 index 83b4948a8..000000000 --- a/openfpga/test_vpr_arch/k6_N10_40nm.xml +++ /dev/null @@ -1,299 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml deleted file mode 100644 index 8476a5155..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_40nm.xml +++ /dev/null @@ -1,441 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml deleted file mode 100644 index 1fb82be72..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml +++ /dev/null @@ -1,644 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml deleted file mode 100644 index e0d7ce812..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_mem16K_40nm.xml +++ /dev/null @@ -1,739 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml deleted file mode 100644 index 146a170e5..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_40nm.xml +++ /dev/null @@ -1,441 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml deleted file mode 100644 index 8f1dfd10e..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml +++ /dev/null @@ -1,644 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml deleted file mode 100644 index 8254a0583..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_40nm.xml +++ /dev/null @@ -1,739 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml deleted file mode 100644 index 35eedb327..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_aib_40nm.xml +++ /dev/null @@ -1,805 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - aib.tx_clk aib.tx_data aib.rx_clk aib.rx_data - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml deleted file mode 100644 index d23c34960..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_multi_io_capacity_40nm.xml +++ /dev/null @@ -1,773 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io_top.outpad io_top.inpad - - - - - - - - - - - io_right.outpad io_right.inpad - - - - - - - - - - - io_bottom.outpad io_bottom.inpad - - - - - - - - - - - io_left.outpad io_left.inpad - - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml deleted file mode 100644 index bb06c5f39..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_mem16K_reduced_io_40nm.xml +++ /dev/null @@ -1,742 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml deleted file mode 100644 index 1bb8ffe23..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_chain_wide_mem16K_40nm.xml +++ /dev/null @@ -1,739 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml deleted file mode 100644 index 77dedbcb0..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_chain_40nm.xml +++ /dev/null @@ -1,696 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin clb.regin - clb.O[9:0] clb.I[19:0] - clb.cout clb.regout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml deleted file mode 100644 index f83919c7c..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_40nm.xml +++ /dev/null @@ -1,734 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin clb.regin clb.scin - clb.O[9:0] clb.I[19:0] - clb.cout clb.regout clb.scout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml deleted file mode 100644 index 7e4cf8e7a..000000000 --- a/openfpga/test_vpr_arch/k6_frac_N10_tileable_thru_channel_adder_chain_mem16K_40nm.xml +++ /dev/null @@ -1,734 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - io.outpad io.inpad - - - - - - - - - - - - - - - - - - - clb.clk - clb.cin - clb.O[9:0] clb.I[19:0] - clb.cout clb.O[19:10] clb.I[39:20] - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1 - 1 1 1 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 235e-12 - 235e-12 - 235e-12 - 235e-12 - 235e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 195e-12 - 195e-12 - 195e-12 - 195e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - 261e-12 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga b/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga similarity index 50% rename from openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga rename to openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga index fbcdda185..5bac56d00 100644 --- a/openfpga/test_script/and_k6_frac_tileable_adder_column_chain.openfpga +++ b/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga @@ -1,17 +1,16 @@ # Run VPR for the 'and' design -vpr ./test_vpr_arch/k6_frac_N10_tileable_adder_chain_40nm.xml ./test_blif/and.blif --route_chan_width 40 --clock_modeling route #--write_rr_graph example_rr_graph.xml +#--write_rr_graph example_rr_graph.xml +vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --device ${OPENFPGA_VPR_DEVICE_LAYOUT} --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} # Read OpenFPGA architecture definition -read_openfpga_arch -f ./test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +read_openfpga_arch -f ${OPENFPGA_ARCH_FILE} -# Write out the architecture XML as a proof -#write_openfpga_arch -f ./arch_echo.xml +# Read OpenFPGA simulation settings +read_openfpga_simulation_setting -f ${OPENFPGA_SIM_SETTING_FILE} # Annotate the OpenFPGA architecture to VPR data base -link_openfpga_arch --activity_file ./test_blif/and.act --sort_gsb_chan_node_in_edges #--verbose - -# Write GSB to XML for debugging -write_gsb_to_xml --file /var/tmp/xtang/openfpga_test_src/gsb_xml +# to debug use --verbose options +link_openfpga_arch --activity_file ${ACTIVITY_FILE} --sort_gsb_chan_node_in_edges # Check and correct any naming conflicts in the BLIF netlist check_netlist_naming_conflict --fix --report ./netlist_renaming.xml @@ -20,28 +19,35 @@ check_netlist_naming_conflict --fix --report ./netlist_renaming.xml pb_pin_fixup --verbose # Apply fix-up to Look-Up Table truth tables based on packing results -lut_truth_table_fixup #--verbose +lut_truth_table_fixup -# Build the module graph +# Build the module graph # - Enabled compression on routing architecture modules -# - Enable pin duplication on grid modules -build_fabric --compress_routing --duplicate_grid_pin --verbose +# - Enable pin duplication on grid modules +build_fabric --compress_routing #--verbose + +# Write the fabric hierarchy of module graph to a file +# This is used by hierarchical PnR flows +write_fabric_hierarchy --file ./fabric_hierarchy.txt # Repack the netlist to physical pbs # This must be done before bitstream generator and testbench generation # Strongly recommend it is done after all the fix-up have been applied repack #--verbose -# Build the bitstream +# Build the bitstream # - Output the fabric-independent bitstream to a file -build_architecture_bitstream --verbose --file /var/tmp/xtang/openfpga_test_src/fabric_indepenent_bitstream.xml +build_architecture_bitstream --verbose --write_file fabric_independent_bitstream.xml # Build fabric-dependent bitstream build_fabric_bitstream --verbose +# Write fabric-dependent bitstream +write_fabric_bitstream --file fabric_bitstream.xml --format xml + # Write the Verilog netlist for FPGA fabric # - Enable the use of explicit port mapping in Verilog netlist -write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose +write_fabric_verilog --file ./SRC --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose # Write the Verilog testbench for FPGA fabric # - We suggest the use of same output directory as fabric Verilog netlists @@ -49,14 +55,20 @@ write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src/SRC --explicit_port # - Enable top-level testbench which is a full verification including programming circuit and core logic of FPGA # - Enable pre-configured top-level testbench which is a fast verification skipping programming phase # - Simulation ini file is optional and is needed only when you need to interface different HDL simulators using openfpga flow-run scripts -write_verilog_testbench --file /var/tmp/xtang/openfpga_test_src/SRC --reference_benchmark_file_path /var/tmp/xtang/and.v --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini /var/tmp/xtang/openfpga_test_src/simulation_deck.ini +write_verilog_testbench --file ./SRC --reference_benchmark_file_path ${REFERENCE_VERILOG_TESTBENCH} --print_top_testbench --print_preconfig_top_testbench --print_simulation_ini ./SimulationDeck/simulation_deck.ini --explicit_port_mapping # Write the SDC files for PnR backend -# - Turn on every options here -write_pnr_sdc --file /var/tmp/xtang/openfpga_test_src/SDC +# - Turn on every options here +write_pnr_sdc --file ./SDC + +# Write SDC to disable timing for configure ports +write_sdc_disable_timing_configure_ports --file ./SDC/disable_configure_ports.sdc # Write the SDC to run timing analysis for a mapped FPGA fabric -write_analysis_sdc --file /var/tmp/xtang/openfpga_test_src/SDC_analysis +write_analysis_sdc --file ./SDC_analysis # Finish and exit OpenFPGA exit + +# Note : +# To run verification at the end of the flow maintain source in ./SRC directory diff --git a/openfpga_flow/VerilogNetlists/adder.v b/openfpga_flow/VerilogNetlists/adder.v index da288c9b9..fa13384d9 100644 --- a/openfpga_flow/VerilogNetlists/adder.v +++ b/openfpga_flow/VerilogNetlists/adder.v @@ -1,19 +1,20 @@ -//------ Module: sram6T_blwl -----// -//------ Verilog file: sram.v -----// -//------ Author: Xifan TANG -----// -module adder( -input [0:0] a, // Input a -input [0:0] b, // Input b -input [0:0] cin, // Input cin -output [0:0] cout, // Output carry -output [0:0] sumout // Output sum -); -//wire[1:0] int_calc; +//----------------------------------------------------- +// Design Name : Multi-bit Full Adder +// File Name : adder.v +// Coder : Xifan TANG +//----------------------------------------------------- -//assign int_calc = a + b + cin; -//assign cout = int_calc[1]; -//assign sumout = int_calc[0]; - assign sumout = a ^ b ^ cin; - assign cout = (a & b) | (a & cin) | (b & cin); +//----------------------------------------------------- +// Function : A 1-bit full adder +//----------------------------------------------------- +module ADDF( + input [0:0] A, // Input a + input [0:0] B, // Input b + input [0:0] CI, // Input cin + output [0:0] CO, // Output carry + output [0:0] SUM // Output sum +); + assign SUM = A ^ B ^ CI; + assign CO = (A & B) | (A & CI) | (B & CI); endmodule diff --git a/openfpga_flow/VerilogNetlists/aib.v b/openfpga_flow/VerilogNetlists/aib.v index 2ebfd5cea..8d1b9e6da 100644 --- a/openfpga_flow/VerilogNetlists/aib.v +++ b/openfpga_flow/VerilogNetlists/aib.v @@ -5,12 +5,12 @@ // Coder : Xifan Tang //----------------------------------------------------- -module aib ( - input tx_clk, - input rx_clk, - inout[0:79] pad, - input[0:79] tx_data, - output[0:79] rx_data); +module AIB ( + input TX_CLK, + input RX_CLK, + inout[0:79] PAD, + input[0:79] TX_DATA, + output[0:79] RX_DATA); // May add the logic function of a real AIB // Refer to the offical AIB github diff --git a/openfpga_flow/VerilogNetlists/config_latch.v b/openfpga_flow/VerilogNetlists/config_latch.v deleted file mode 100644 index 6cbe5657e..000000000 --- a/openfpga_flow/VerilogNetlists/config_latch.v +++ /dev/null @@ -1,38 +0,0 @@ -//----------------------------------------------------- -// Design Name : config_latch -// File Name : config_latch.v -// Function : A Configurable Latch where data storage -// can be updated at rising clock edge -// when wl is enabled -// Coder : Xifan TANG -//----------------------------------------------------- -module config_latch ( - input reset, // Reset input - input clk, // Clock Input - input wl, // Data Enable - input bl, // Data Input - output Q, // Q output - output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset) begin - if (reset) begin - q_reg <= 1'b0; - end else if (1'b1 == wl) begin - q_reg <= bl; - end -end - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~q_reg; -`else -assign Q = 1'bZ; -assign Qb = !Q; -`endif - -endmodule diff --git a/openfpga_flow/VerilogNetlists/dff.v b/openfpga_flow/VerilogNetlists/dff.v new file mode 100644 index 000000000..8803e1239 --- /dev/null +++ b/openfpga_flow/VerilogNetlists/dff.v @@ -0,0 +1,311 @@ +//----------------------------------------------------- +// Design Name : D-type Flip-flops +// File Name : ff.v +// Coder : Xifan TANG +//----------------------------------------------------- + +//----------------------------------------------------- +// Function : A native D-type flip-flop +//----------------------------------------------------- +module DFF ( + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (posedge CK) begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +//----------------------------------------------------- +module DFFR ( + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST) +if (RST) begin + q_reg <= 1'b0; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active low reset +//----------------------------------------------------- +module DFFRN ( + input RSTN, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or negedge RSTN) +if (~RSTN) begin + q_reg <= 1'b0; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high set +//----------------------------------------------------- +module DFFS ( + input SET, // Set input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge SET) +if (SET) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active low set +//----------------------------------------------------- +module DFFSN ( + input SETN, // Set input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or negedge SETN) +if (~SETN) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - asynchronous active high set +//----------------------------------------------------- +module DFFSR ( + input SET, // set input + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q, // Q output + output QN // QB output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RST) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - asynchronous active high set +//----------------------------------------------------- +module DFFSRQ ( + input SET, // set input + input RST, // Reset input + input CK, // Clock Input + input D, // Data Input + output Q // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RST) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else begin + q_reg <= D; +end + +assign Q = q_reg; + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - asynchronous active high set +// - scan-chain input +// - a scan-chain enable +//----------------------------------------------------- +module SDFFSR ( + input SET, // Set input + input RST, // Reset input + input CK, // Clock Input + input SE, // Scan-chain Enable + input D, // Data Input + input SI, // Scan-chain input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RST) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else if (SE) begin + q_reg <= SI; +end else begin + q_reg <= D; +end + +`ifndef ENABLE_FORMAL_VERIFICATION +// Wire q_reg to Q + assign Q = q_reg; + assign QN = !Q; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule //End Of Module + +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - asynchronous active high set +// - scan-chain input +// - a scan-chain enable +//----------------------------------------------------- +module SDFFSRQ ( + input SET, // Set input + input RST, // Reset input + input CK, // Clock Input + input SE, // Scan-chain Enable + input D, // Data Input + input SI, // Scan-chain input + output Q // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST or posedge SET) +if (RST) begin + q_reg <= 1'b0; +end else if (SET) begin + q_reg <= 1'b1; +end else if (SE) begin + q_reg <= SI; +end else begin + q_reg <= D; +end + +assign Q = q_reg; + +endmodule //End Of Module diff --git a/openfpga_flow/VerilogNetlists/ff.v b/openfpga_flow/VerilogNetlists/ff.v deleted file mode 100644 index 2f2477f24..000000000 --- a/openfpga_flow/VerilogNetlists/ff.v +++ /dev/null @@ -1,146 +0,0 @@ -//----------------------------------------------------- -// Design Name : static_dff -// File Name : ff.v -// Function : D flip-flop with asyn reset and set -// Coder : Xifan TANG -//----------------------------------------------------- -//------ Include defines: preproc flags ----- -// `include "./SRC/fpga_defines.v" -module static_dff ( -/* Global ports go first */ -input set, // set input -input reset, // Reset input -input clk, // Clock Input -/* Local ports follow */ -input D, // Data Input -output Q // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset or posedge set) -if (reset) begin - q_reg <= 1'b0; -end else if (set) begin - q_reg <= 1'b1; -end else begin - q_reg <= D; -end - -// Wire q_reg to Q -assign Q = q_reg; - -endmodule //End Of Module static_dff - -module scan_chain_ff ( -/* Global ports go first */ -input set, // set input -input reset, // Reset input -input clk, // Clock Input -input TESTEN, // Clock Input -/* Local ports follow */ -input D, // Data Input -input DI, // Scan Chain Data Input -output Q // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset or posedge set) -if (reset) begin - q_reg <= 1'b0; -end else if (set) begin - q_reg <= 1'b1; -end else if (TESTEN) begin - q_reg <= DI; -end else begin - q_reg <= D; -end - -// Wire q_reg to Q -assign Q = q_reg; - -endmodule //End Of Module static_dff - - -//----------------------------------------------------- -// Design Name : scan_chain_dff -// File Name : ff.v -// Function : D flip-flop with asyn reset and set -// Coder : Xifan TANG -//----------------------------------------------------- -module sc_dff ( -/* Global ports go first */ -input set, // set input -input reset, // Reset input -input clk, // Clock Input -/* Local ports follow */ -input D, // Data Input -output Q, // Q output -output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset or posedge set) -if (reset) begin - q_reg <= 1'b0; -end else if (set) begin - q_reg <= 1'b1; -end else begin - q_reg <= D; -end - -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~Q; - -endmodule //End Of Module static_dff - -//----------------------------------------------------- -// Design Name : scan_chain_dff compact -// File Name : ff.v -// Function : Scan-chain D flip-flop without reset and set //Modified to fit Edouards architecture -// Coder : Xifan TANG -//----------------------------------------------------- -module sc_dff_compact ( -/* Global ports go first */ -input reset, // Reset input -//input set, // set input -input clk, // Clock Input -/* Local ports follow */ -input D, // Data Input -output Q, // Q output -output Qb // Q output -); -//------------Internal Variables-------- -reg q_reg; - -//-------------Code Starts Here--------- -always @ ( posedge clk or posedge reset /*or posedge set*/) -if (reset) begin - q_reg <= 1'b0; -//end else if (set) begin -// q_reg <= 1'b1; -end else begin - q_reg <= D; -end -/* -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~Q; -*/ - -`ifndef ENABLE_FORMAL_VERIFICATION -// Wire q_reg to Q -assign Q = q_reg; -assign Qb = ~q_reg; -`else -assign Q = 1'bZ; -assign Qb = !Q; -`endif - -endmodule //End Of Module static_dff diff --git a/openfpga_flow/VerilogNetlists/gpio.v b/openfpga_flow/VerilogNetlists/gpio.v new file mode 100644 index 000000000..5fb318f3d --- /dev/null +++ b/openfpga_flow/VerilogNetlists/gpio.v @@ -0,0 +1,20 @@ +//----------------------------------------------------- +// Design Name : General Purpose I/Os +// File Name : gpio.v +// Coder : Xifan TANG +//----------------------------------------------------- + +//----------------------------------------------------- +// Function : A minimum general purpose I/O +//----------------------------------------------------- +module GPIO ( + input A, // Data output + output Y, // Data input + inout PAD, // bi-directional pad + input DIR // direction control +); + //----- when direction enabled, the signal is propagated from PAD to data input + assign Y = DIR ? PAD : 1'bz; + //----- when direction is disabled, the signal is propagated from data out to pad + assign PAD = DIR ? 1'bz : A; +endmodule diff --git a/openfpga_flow/VerilogNetlists/io.v b/openfpga_flow/VerilogNetlists/io.v deleted file mode 100644 index 9fccdd23d..000000000 --- a/openfpga_flow/VerilogNetlists/io.v +++ /dev/null @@ -1,16 +0,0 @@ -//------ Module: iopad -----// -//------ Verilog file: io.v -----// -//------ Author: Xifan TANG -----// -module iopad( -//input zin, // Set output to be Z -input outpad, // Data output -output inpad, // Data input -inout pad, // bi-directional pad -input en // enable signal to control direction of iopad -//input direction_inv // enable signal to control direction of iopad -); - //----- when direction enabled, the signal is propagated from pad to din - assign inpad = en ? pad : 1'bz; - //----- when direction is disabled, the signal is propagated from dout to pad - assign pad = en ? 1'bz : outpad; -endmodule diff --git a/openfpga_flow/VerilogNetlists/latch.v b/openfpga_flow/VerilogNetlists/latch.v new file mode 100644 index 000000000..f2b0f2f09 --- /dev/null +++ b/openfpga_flow/VerilogNetlists/latch.v @@ -0,0 +1,255 @@ +//----------------------------------------------------- +// Design Name : config_latch +// File Name : config_latch.v +// Coder : Xifan TANG +//----------------------------------------------------- + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +//----------------------------------------------------- +module LATCH ( + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (WE or D) begin + if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-high reset signal +//----------------------------------------------------- +module LATCHR ( + input RST, // Reset signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (RST or WE or D) begin + if (RST) begin + q_reg <= 1'b0; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-low reset signal +//----------------------------------------------------- +module LATCHRN ( + input RSTN, // Reset signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (RSTN or WE or D) begin + if (~RSTN) begin + q_reg <= 1'b0; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-high set signal +//----------------------------------------------------- +module LATCHS ( + input SET, // Set signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (SET or WE or D) begin + if (SET) begin + q_reg <= 1'b1; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-low set signal +//----------------------------------------------------- +module LATCHSN ( + input SETN, // Set signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (SETN or WE or D) begin + if (~SETN) begin + q_reg <= 1'b1; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-high reset signal +// - an active-high set signal +//----------------------------------------------------- +module LATCHSR ( + input RST, // Reset signal + input SET, // Set signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (RST or SET or WE or D) begin + if (RST) begin + q_reg <= 1'b0; + end else if (SET) begin + q_reg <= 1'b1; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A Configurable Latch with +// - an active-high write enable signal +// - an active-high reset signal +// - an active-high set signal +//----------------------------------------------------- +module LATCHSNRN ( + input RSTN, // Reset signal + input SETN, // Set signal + input WE, // Write enable + input D, // Data input + output Q, // Q output + output QN // Q negative output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ (RSTN or SETN or WE or D) begin + if (~RSTN) begin + q_reg <= 1'b0; + end else if (~SETN) begin + q_reg <= 1'b1; + end else if (1'b1 == WE) begin + q_reg <= D; + end +end + +// Wire q_reg to Q +`ifndef ENABLE_FORMAL_VERIFICATION + assign Q = q_reg; + assign QN = ~q_reg; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + diff --git a/openfpga_flow/VerilogNetlists/lb_tb.v b/openfpga_flow/VerilogNetlists/lb_tb.v deleted file mode 100644 index 705970fd6..000000000 --- a/openfpga_flow/VerilogNetlists/lb_tb.v +++ /dev/null @@ -1,199 +0,0 @@ -//----------------------------------------------------- -// Design Name : testbench for logic blocks -// File Name : lb_tb.v -// Function : Configurable logic block -// Coder : Xifan TANG -//----------------------------------------------------- -//----- Time scale: simulation time step and accuracy ----- -`timescale 1ns / 1ps - -module lb_tb; -// Parameters -parameter SIZE_IN = 40; //---- MUX input size -parameter SIZE_OUT = 10; //---- MUX input size -parameter SIZE_RESERV_BLWL = 49 + 1; //---- MUX input size -parameter SIZE_BLWL = 1019 - 310 + 1; //---- MUX input size -parameter prog_clk_period = 1; // [ns] half clock period -parameter op_clk_period = 1; // [ns] half clock period -parameter config_period = 2 * prog_clk_period; // [ns] One full clock period -parameter operating_period = SIZE_IN * 2 * op_clk_period; // [ns] One full clock period - -// Ports -wire [0:SIZE_IN-1] lb_in; -wire [0:SIZE_IN-1] lb_out; -wire lb_clk; -wire [0:SIZE_RESERV_BLWL-1] reserv_bl; -wire [0:SIZE_RESERV_BLWL-1] reserv_wl; -wire [0:SIZE_BLWL-1] bl; -wire [0:SIZE_BLWL-1] wl; -wire prog_EN; -wire prog_ENb; -wire zin; -wire nequalize; -wire read; -wire clk; -wire Reset; -wire Set; -// Clocks -wire prog_clock; -wire op_clock; - -// Registered port -reg [0:SIZE_IN-1] lb_in_reg; -reg [0:SIZE_RESERV_BLWL-1] reserv_bl_reg; -reg [0:SIZE_RESERV_BLWL-1] reserv_wl_reg; -reg [0:SIZE_BLWL-1] bl_reg; -reg [0:SIZE_BLWL-1] wl_reg; -reg prog_clock_reg; -reg op_clock_reg; - -// Config done signal; -reg config_done; -// Temp register for rotating shift -reg temp; - -// Unit under test -grid_1__1_ U0 ( -zin, -nequalize, -read, -clk, -Reset, -Set, -prog_ENb, -prog_EN, -// Top inputs -lb_in[0], lb_in[4], lb_in[8], lb_in[12], lb_in[16], -lb_in[20], lb_in[24], lb_in[28], lb_in[32], lb_in[36], -// Top outputs -lb_out[0], lb_out[4], lb_out[8], -// Right inputs -lb_in[1], lb_in[5], lb_in[9], lb_in[13], lb_in[17], -lb_in[21], lb_in[25], lb_in[29], lb_in[33], lb_in[37], -// Right outputs -lb_out[1], lb_out[5], lb_out[9], -// Bottom inputs -lb_in[2], lb_in[6], lb_in[10], lb_in[14], lb_in[18], -lb_in[22], lb_in[26], lb_in[30], lb_in[34], lb_in[38], -// Bottom outputs -lb_out[2], lb_out[6], -// Bottom inputs -lb_clk, -// left inputs -lb_in[3], lb_in[7], lb_in[11], lb_in[15], lb_in[19], -lb_in[23], lb_in[27], lb_in[31], lb_in[35], lb_in[39], -// left outputs -lb_out[3], lb_out[7], -reserv_bl, reserv_wl, -bl, wl -); - -// Task: assign BL and WL values -task prog_lb_blwl; - begin - @(posedge prog_clock); - // Rotate left shift - temp = reserv_bl_reg[SIZE_RESERV_BLWL-1]; - //bl_reg = bl_reg >> 1; - reserv_bl_reg[1:SIZE_RESERV_BLWL-1] = reserv_bl_reg[0:SIZE_RESERV_BLWL-2]; - reserv_bl_reg[0] = temp; - end -endtask - -// Task: assign inputs -task op_lb_in; - begin - @(posedge op_clock); - temp = lb_in_reg[SIZE_IN-1]; - lb_in_reg[1:SIZE_IN-1] = lb_in_reg[0:SIZE_IN-2]; - lb_in_reg[0] = temp; - end -endtask - -// Configuration done signal -initial -begin - config_done = 1'b0; -end -// Enabled during config_period, Disabled during op_period -always -begin - #config_period config_done = ~config_done; - #operating_period config_done = ~config_done; -end - -// Programming clocks -initial -begin - prog_clock_reg = 1'b0; -end -always -begin - #prog_clk_period prog_clock_reg = ~prog_clock_reg; -end - -// Operating clocks -initial -begin - op_clock_reg = 1'b0; -end -always -begin - #op_clk_period op_clock_reg = ~op_clock_reg; -end - -// Programming and Operating clocks -assign prog_clock = prog_clock_reg & (~config_done); -assign op_clock = op_clock_reg & config_done; - -// Programming Enable signals -assign prog_EN = prog_clock & (~config_done); -assign prog_ENb = ~prog_EN; - -// Programming phase: BL/WL -initial -begin - // Initialize BL/WL registers - reserv_bl_reg = {SIZE_RESERV_BLWL {1'b0}}; - reserv_bl_reg[0] = 1'b1; - reserv_wl_reg = {SIZE_RESERV_BLWL {1'b0}}; - // Reserved BL/WL - bl_reg = {SIZE_BLWL {1'b0}}; - wl_reg = {SIZE_BLWL {1'b1}}; - //wl_reg[SIZE_BLWL-1] = 1'b1; -end -always wait (~config_done) // Only invoked when config_done is 0 -begin - // Propagate input 1 to the output - // BL[0] = 1, WL[4] = 1 - prog_lb_blwl; -end - -// Operating Phase -initial -begin - lb_in_reg = {SIZE_IN {1'b0}}; - lb_in_reg[0] = 1'b1; // Last bit is 1 initially -end -always wait (config_done) // Only invoked when config_done is 1 -begin - /* Update inputs */ - op_lb_in; -end - -// Wire ports -assign lb_in = lb_in_reg; -assign reserv_bl = reserv_bl_reg; -assign reserv_wl = reserv_wl_reg; -assign bl = bl_reg; -assign wl = wl_reg; - -// Constant ports -assign zin = 1'b0; -assign nequalize = 1'b1; -assign read = 1'b0; -assign clk = op_clock; -assign Reset = ~config_done; -assign Set = 1'b0; - -endmodule diff --git a/openfpga_flow/VerilogNetlists/sram.v b/openfpga_flow/VerilogNetlists/sram.v index c27dbeebe..86f3ddf99 100644 --- a/openfpga_flow/VerilogNetlists/sram.v +++ b/openfpga_flow/VerilogNetlists/sram.v @@ -1,31 +1,31 @@ //----------------------------------------------------- // Design Name : sram_blwl // File Name : sram.v -// Function : A SRAM cell is is accessible -// when wl is enabled // Coder : Xifan TANG //----------------------------------------------------- -module sram_blwl( -input reset, // Word line control signal -input wl, // Word line control signal -input bl, // Bit line control signal -output out, // Data output -output outb // Data output + + +//----------------------------------------------------- +// Function : A SRAM cell with write enable +//----------------------------------------------------- +module SRAM( + input WE, // Word line control signal as write enable + input D, // Bit line control signal + output Q, // Data output + output QN // Data output ); //----- local variable need to be registered reg data; //----- when wl is enabled, we can read in data from bl - always @(bl, wl) + always @(WE or D) begin - if (1'b1 == reset) begin - data <= 1'b0; - end else if ((1'b1 == bl)&&(1'b1 == wl)) begin + if ((1'b1 == D)&&(1'b1 == WE)) begin //----- Cases to program internal memory bit //----- case 1: bl = 1, wl = 1, a -> 0 data <= 1'b1; - end else if ((1'b0 == bl)&&(1'b1 == wl)) begin + end else if ((1'b0 == D)&&(1'b1 == WE)) begin //----- case 2: bl = 0, wl = 1, a -> 0 data <= 1'b0; end @@ -33,57 +33,276 @@ output outb // Data output `ifndef ENABLE_FORMAL_VERIFICATION // Wire q_reg to Q - assign out = data; - assign outb = ~data; + assign Q = data; + assign QN = ~data; `else - assign out = 1'bZ; - assign outb = !out; + assign Q = 1'bZ; + assign QN = !Q; `endif endmodule - -//------ Module: sram6T_blwl -----// -//------ Verilog file: sram.v -----// -//------ Author: Xifan TANG -----// -module sram6T_blwl( -//input read, -//input nequalize, -input din, // Data input -output dout, // Data output -output doutb, // Data output -input bl, // Bit line control signal -input wl, // Word line control signal -input blb // Inverted Bit line control signal +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-high set +// - a write-enable +//----------------------------------------------------- +module SRAMS( + input SET, // active-high set signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output ); + //----- local variable need to be registered - reg a; + reg data; //----- when wl is enabled, we can read in data from bl - always @(bl, wl) + always @(D or WE) begin + if (1'b1 == SET) begin + data <= 1'b1; + end else if ((1'b1 == D)&&(1'b1 == WE)) begin //----- Cases to program internal memory bit //----- case 1: bl = 1, wl = 1, a -> 0 - if ((1'b1 == bl)&&(1'b1 == wl)) begin - a <= 1'b1; - end + data <= 1'b1; + end else if ((1'b0 == D)&&(1'b1 == WE)) begin //----- case 2: bl = 0, wl = 1, a -> 0 - if ((1'b0 == bl)&&(1'b1 == wl)) begin - a <= 1'b0; + data <= 1'b0; end end - // dout is short-wired to din - assign dout = a; - //---- doutb is always opposite to dout - assign doutb = ~dout; -`ifdef ENABLE_SIGNAL_INITIALIZATION - initial begin - $deposit(a, $random); - end +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign Q = data; + assign QN = ~data; +`else + assign Q = 1'bZ; + assign QN = !Q; `endif + endmodule +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-low set +// - a write-enable +//----------------------------------------------------- +module SRAMSN( + input SETN, // active-low set signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output +); + + //----- local variable need to be registered + reg data; + + //----- when wl is enabled, we can read in data from bl + always @(D or WE) + begin + if (1'b0 == SETN) begin + data <= 1'b1; + end else if ((1'b1 == D)&&(1'b1 == WE)) begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + data <= 1'b1; + end else if ((1'b0 == D)&&(1'b1 == WE)) begin + //----- case 2: bl = 0, wl = 1, a -> 0 + data <= 1'b0; + end + end + +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign Q = data; + assign QN = ~data; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-high reset +// - a write-enable +//----------------------------------------------------- +module SRAMR( + input RST, // active-high reset signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output +); + + //----- local variable need to be registered + reg data; + + //----- when wl is enabled, we can read in data from bl + always @(D or WE) + begin + if (1'b1 == RST) begin + data <= 1'b0; + end else if ((1'b1 == D)&&(1'b1 == WE)) begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + data <= 1'b1; + end else if ((1'b0 == D)&&(1'b1 == WE)) begin + //----- case 2: bl = 0, wl = 1, a -> 0 + data <= 1'b0; + end + end + +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign Q = data; + assign QN = ~data; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-low reset +// - a write-enable +//----------------------------------------------------- +module SRAMRN( + input RSTN, // active-low reset signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output +); + + //----- local variable need to be registered + reg data; + + //----- when wl is enabled, we can read in data from bl + always @(D or WE) + begin + if (1'b0 == RSTN) begin + data <= 1'b0; + end else if ((1'b1 == D)&&(1'b1 == WE)) begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + data <= 1'b1; + end else if ((1'b0 == D)&&(1'b1 == WE)) begin + //----- case 2: bl = 0, wl = 1, a -> 0 + data <= 1'b0; + end + end + +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign Q = data; + assign QN = ~data; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-high reset +// - an active-high set +// - a write-enable +//----------------------------------------------------- +module SRAMSR( + input RST, // active-high reset signal + input SET, // active-high set signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output +); + + //----- local variable need to be registered + reg data; + + //----- when wl is enabled, we can read in data from bl + always @(D or WE) + begin + if (1'b1 == RST) begin + data <= 1'b0; + end else if (1'b1 == SET) begin + data <= 1'b1; + end else if ((1'b1 == D)&&(1'b1 == WE)) begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + data <= 1'b1; + end else if ((1'b0 == D)&&(1'b1 == WE)) begin + //----- case 2: bl = 0, wl = 1, a -> 0 + data <= 1'b0; + end + end + +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign Q = data; + assign QN = ~data; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + +//----------------------------------------------------- +// Function : A SRAM cell with +// - an active-low reset +// - an active-low set +// - a write-enable +//----------------------------------------------------- +module SRAMSNRN( + input RSTN, // active-low reset signal + input SETN, // active-low set signal + input WE, // Word line control signal as write enable + input D, // Bit line control signal as data input + output Q, // Data output + output QN // Data output +); + + //----- local variable need to be registered + reg data; + + //----- when wl is enabled, we can read in data from bl + always @(D or WE) + begin + if (1'b0 == RSTN) begin + data <= 1'b0; + end else if (1'b0 == SETN) begin + data <= 1'b1; + end else if ((1'b1 == D)&&(1'b1 == WE)) begin + //----- Cases to program internal memory bit + //----- case 1: bl = 1, wl = 1, a -> 0 + data <= 1'b1; + end else if ((1'b0 == D)&&(1'b1 == WE)) begin + //----- case 2: bl = 0, wl = 1, a -> 0 + data <= 1'b0; + end + end + +`ifndef ENABLE_FORMAL_VERIFICATION + // Wire q_reg to Q + assign Q = data; + assign QN = ~data; +`else + assign Q = 1'bZ; + assign QN = !Q; +`endif + +endmodule + + module sram6T_rram( input read, input nequalize, diff --git a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml index f1f0a7362..07a874f86 100644 --- a/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml +++ b/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml @@ -2,7 +2,7 @@ - Architecture independent bitstream - Author: Xifan TANG - Organization: University of Utah - - Date: Mon Jul 27 15:47:36 2020 + - Date: Thu Sep 24 20:16:32 2020 --> @@ -11,7 +11,7 @@ - + @@ -19,7 +19,7 @@ - + @@ -64,7 +64,7 @@ - + @@ -72,7 +72,7 @@ - + @@ -117,7 +117,7 @@ - + @@ -125,7 +125,7 @@ - + @@ -170,7 +170,7 @@ - + @@ -178,7 +178,7 @@ - + @@ -563,7 +563,7 @@ - + @@ -571,7 +571,7 @@ - + @@ -616,7 +616,7 @@ - + @@ -624,7 +624,7 @@ - + @@ -669,7 +669,7 @@ - + @@ -677,7 +677,7 @@ - + @@ -722,7 +722,7 @@ - + @@ -730,7 +730,7 @@ - + @@ -1115,7 +1115,7 @@ - + @@ -1123,7 +1123,7 @@ - + @@ -1168,7 +1168,7 @@ - + @@ -1176,7 +1176,7 @@ - + @@ -1221,7 +1221,7 @@ - + @@ -1229,7 +1229,7 @@ - + @@ -1274,7 +1274,7 @@ - + @@ -1282,24 +1282,24 @@ - + - + - + - + - - + + - + - + - + @@ -1703,7 +1703,7 @@ - + @@ -1711,7 +1711,7 @@ - + @@ -1756,7 +1756,7 @@ - + @@ -1764,7 +1764,7 @@ - + @@ -1809,7 +1809,7 @@ - + @@ -1817,7 +1817,7 @@ - + @@ -1862,7 +1862,7 @@ - + @@ -1870,7 +1870,7 @@ - + @@ -2253,13 +2253,13 @@ - + - + @@ -2269,13 +2269,13 @@ - + - + @@ -2285,13 +2285,13 @@ - + - + @@ -2301,13 +2301,13 @@ - + - + @@ -2317,13 +2317,13 @@ - + - + @@ -2333,13 +2333,13 @@ - + - + @@ -2349,13 +2349,13 @@ - + - + @@ -2365,13 +2365,13 @@ - + - + @@ -2383,13 +2383,13 @@ - + - + @@ -2399,13 +2399,13 @@ - + - + @@ -2415,13 +2415,13 @@ - + - + @@ -2431,13 +2431,13 @@ - + - + @@ -2447,13 +2447,13 @@ - + - + @@ -2463,13 +2463,13 @@ - + - + @@ -2479,13 +2479,13 @@ - + - + @@ -2495,13 +2495,13 @@ - + - + @@ -2513,13 +2513,13 @@ - + - + @@ -2529,13 +2529,13 @@ - + - + @@ -2545,13 +2545,13 @@ - + - + @@ -2561,13 +2561,13 @@ - + - + @@ -2577,13 +2577,13 @@ - + - + @@ -2593,13 +2593,13 @@ - + - + @@ -2609,13 +2609,13 @@ - + - + @@ -2625,13 +2625,13 @@ - + - + @@ -2643,13 +2643,13 @@ - + - + @@ -2659,13 +2659,13 @@ - + - + @@ -2675,13 +2675,13 @@ - + - + @@ -2691,13 +2691,13 @@ - + - + @@ -2707,13 +2707,13 @@ - + - + @@ -2723,13 +2723,13 @@ - + - + @@ -2739,13 +2739,13 @@ - + - + @@ -2755,13 +2755,13 @@ - + - + @@ -2773,13 +2773,13 @@ - + - + @@ -2789,13 +2789,13 @@ - + - + @@ -2805,13 +2805,13 @@ - + - + @@ -2821,13 +2821,13 @@ - + - + @@ -2837,13 +2837,13 @@ - + - + @@ -2853,13 +2853,13 @@ - + - + @@ -2869,13 +2869,13 @@ - + - + @@ -2885,13 +2885,13 @@ - + - + @@ -2903,13 +2903,13 @@ - + - + @@ -2919,13 +2919,13 @@ - + - + @@ -2935,13 +2935,13 @@ - + - + @@ -2951,13 +2951,13 @@ - + - + @@ -2967,13 +2967,13 @@ - + - + @@ -2983,13 +2983,13 @@ - + - + @@ -2999,13 +2999,13 @@ - + - + @@ -3015,13 +3015,13 @@ - + - + @@ -3033,13 +3033,13 @@ - + - + @@ -3049,13 +3049,13 @@ - + - + @@ -3065,13 +3065,13 @@ - + - + @@ -3081,13 +3081,13 @@ - + - + @@ -3097,13 +3097,13 @@ - + - + @@ -3113,13 +3113,13 @@ - + - + @@ -3129,13 +3129,13 @@ - + - + @@ -3145,13 +3145,13 @@ - + - + @@ -3163,13 +3163,13 @@ - + - + @@ -3179,13 +3179,13 @@ - + - + @@ -3195,13 +3195,13 @@ - + - + @@ -3211,13 +3211,13 @@ - + - + @@ -3227,13 +3227,13 @@ - + - + @@ -3243,13 +3243,13 @@ - + - + @@ -3259,13 +3259,13 @@ - + - + @@ -3275,13 +3275,13 @@ - + - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml index 110ea66a9..e2ce76956 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml @@ -124,15 +124,15 @@ - + - - - - - + + + + + @@ -146,28 +146,27 @@ - + - - - - - + + + + - + - - - - + + + + - + @@ -181,7 +180,7 @@ - + @@ -193,7 +192,7 @@ - + diff --git a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml similarity index 74% rename from openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml rename to openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml index de0602e1e..d8f97ba41 100644 --- a/openfpga/test_openfpga_arch/k6_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml @@ -30,6 +30,7 @@ + @@ -41,6 +42,7 @@ + @@ -52,6 +54,7 @@ + @@ -63,6 +66,7 @@ + @@ -120,50 +124,51 @@ - + - - + + - + - + - + - + - + - - - - - + + + + + + - + - - - - + + + + - + @@ -177,7 +182,7 @@ - + @@ -188,41 +193,8 @@ - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml similarity index 61% rename from openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml rename to openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml index 51e250a8a..427889368 100644 --- a/openfpga/test_openfpga_arch/k6_frac_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml @@ -30,6 +30,7 @@ + @@ -41,6 +42,7 @@ + @@ -52,6 +54,7 @@ + @@ -61,22 +64,9 @@ 10e-12 - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - + @@ -134,53 +124,50 @@ - + - - + + - + - - + + - - - - - - + + + - + - - - - - + + + + + - + - - - - + + + + - + @@ -194,7 +181,7 @@ - + @@ -205,56 +192,8 @@ - - - - - - - - - - - - - - - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml similarity index 60% rename from openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml rename to openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml index 159214507..d03b2d2be 100644 --- a/openfpga/test_openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml @@ -30,6 +30,7 @@ + @@ -41,6 +42,7 @@ + @@ -52,6 +54,7 @@ + @@ -61,22 +64,9 @@ 10e-12 - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - + @@ -134,57 +124,50 @@ - + - - + + - + - - + + - - - - - - + + + - + - - - - - + + + + + - + - - - - - - - - + + + + - + @@ -198,7 +181,7 @@ - + @@ -209,56 +192,8 @@ - - - - - - - - - - - - - - - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml new file mode 100644 index 000000000..fec761135 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml new file mode 100644 index 000000000..dc3c89739 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml index f1db02ad1..a36a863fd 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml @@ -115,15 +115,15 @@ - + - - + + - + @@ -137,28 +137,27 @@ - + - - - + + - + - - - - + + + + - + @@ -172,7 +171,7 @@ - + @@ -184,7 +183,7 @@ - + diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml similarity index 58% rename from openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml rename to openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml index d04318510..762fc1af3 100644 --- a/openfpga/test_openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml @@ -30,6 +30,7 @@ + @@ -41,6 +42,7 @@ + @@ -52,6 +54,7 @@ + @@ -61,22 +64,9 @@ 10e-12 - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - - + + @@ -106,72 +96,70 @@ - + - + - + - + - + - - + + - + - - + + - - - - - - - + + + + - + - + + - - + + - + - - - - + + + + - + @@ -185,7 +173,7 @@ - + @@ -196,56 +184,8 @@ - - - - - - - - - - - - - - - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml similarity index 53% rename from openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml rename to openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml index 59f493a13..c74d0aedb 100644 --- a/openfpga/test_openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml @@ -30,6 +30,7 @@ + @@ -41,6 +42,7 @@ + @@ -52,6 +54,7 @@ + @@ -61,36 +64,22 @@ 10e-12 - - + + + - - + + + - - 10e-12 5e-12 + + 10e-12 5e-12 5e-12 - - 10e-12 5e-12 + + 10e-12 5e-12 5e-12 - - - - - - - - - - @@ -107,72 +96,69 @@ - + - + - + - + - + - - + + - + - - + + - - - - - - - + + + + - + - + - - + + - + - - - - + + + + - + @@ -186,7 +172,7 @@ - + @@ -197,56 +183,8 @@ - - - - - - - - - - - - - - - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml new file mode 100644 index 000000000..3e453fb3f --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml @@ -0,0 +1,190 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml new file mode 100644 index 000000000..78461fadc --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml @@ -0,0 +1,190 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml new file mode 100644 index 000000000..ee990043b --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml @@ -0,0 +1,190 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml index 95359f565..dced448a2 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_fixed_sim_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -146,28 +146,28 @@ - + - + - - + + - + - - - - + + + + - + @@ -181,7 +181,7 @@ - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml similarity index 55% rename from openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml rename to openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml index 65117d199..5d9aee9eb 100644 --- a/openfpga/test_openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml @@ -30,6 +30,7 @@ + @@ -41,6 +42,7 @@ + @@ -52,6 +54,7 @@ + @@ -61,22 +64,9 @@ 10e-12 - - - - - - - - - 10e-12 5e-12 - - - 10e-12 5e-12 - - + @@ -134,64 +124,50 @@ - + - - + + - + - - + + - - - - - - - + + + - + - - - - - + + + + + - + - - - - - - - - - - - - - - + + + + - + @@ -202,13 +178,10 @@ - - - - + @@ -219,67 +192,8 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml index b89a23644..92b7930c7 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -146,29 +146,27 @@ - + - - - - - - + + + + - + - - - - + + + + - + @@ -182,7 +180,7 @@ - + @@ -194,7 +192,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml new file mode 100644 index 000000000..ff3f2e1b0 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml @@ -0,0 +1,202 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml new file mode 100644 index 000000000..7495f9c3b --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml @@ -0,0 +1,200 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml new file mode 100644 index 000000000..0b7f14a25 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml new file mode 100644 index 000000000..f43436de5 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml new file mode 100644 index 000000000..cee0fbc79 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml new file mode 100644 index 000000000..7ba360992 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml @@ -0,0 +1,199 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml index bf96e1aa0..0d03dc6d6 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_powergate_frame_openfpga.xml @@ -36,7 +36,7 @@ - + @@ -130,15 +130,15 @@ - + - - + + - + @@ -152,29 +152,28 @@ - + - - - - - - + + + + + - + - - - - + + + + - + @@ -188,7 +187,7 @@ - + @@ -200,7 +199,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml index 035732d35..3392eef23 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_40nm_standalone_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -146,29 +146,28 @@ - + - - - - - - + + + + + - + - - - - + + + + - + @@ -182,7 +181,7 @@ - + @@ -194,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml index 9ba39b3ce..cf0502130 100644 --- a/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -146,29 +146,28 @@ - + - - - - - - + + + + + - + - - - - + + + + - + @@ -182,7 +181,7 @@ - + @@ -190,7 +189,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml new file mode 100644 index 000000000..6366425e0 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml @@ -0,0 +1,212 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml index ee5c4df5f..ceef842c0 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_40nm_cc_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -161,31 +161,31 @@ - + - + - + - - + + - + - - - - + + + + - + @@ -199,7 +199,7 @@ - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml index 7033f1eda..beeb811e1 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_40nm_cc_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -161,41 +161,41 @@ - + - + - + - - + + - + - - - - + + + + - + - - - - - + + + + + - + @@ -212,7 +212,7 @@ - + @@ -225,8 +225,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml index 508ceab90..aed95c588 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_40nm_frame_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -161,38 +161,37 @@ - + - + - - - - - - + + + + + - + - - - - + + + + - + - - - - - + + + + + @@ -208,7 +207,7 @@ - + @@ -225,7 +224,7 @@ - + @@ -238,8 +237,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml index 8bba60744..f5efbc285 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -161,38 +161,37 @@ - + - + - - - - - - + + + + + - + - - - - + + + + - + - - - - - + + + + + @@ -208,7 +207,7 @@ - + @@ -229,7 +228,7 @@ - + @@ -242,8 +241,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml index eb5e3c659..af193a385 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_frac_dsp32_40nm_frame_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -161,38 +161,37 @@ - + - + - - - - - - + + + + + - + - - - - + + + + - + - - - - - + + + + + @@ -214,11 +213,11 @@ - + - + @@ -235,7 +234,7 @@ - + @@ -248,8 +247,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml index 81e60ee3a..9c8e66a87 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_40nm_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -146,28 +146,28 @@ - + - + - - + + - + - - - - + + + + - + @@ -181,7 +181,7 @@ - + @@ -193,7 +193,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml index 06ef4506d..e0e8cd461 100644 --- a/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_N10_intermediate_buffer_40nm_openfpga.xml @@ -124,15 +124,15 @@ - + - - + + - + @@ -147,28 +147,28 @@ - + - + - - + + - + - - - - + + + + - + @@ -182,7 +182,7 @@ - + @@ -194,7 +194,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml index ae4e5d1e1..3afe5a693 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -161,31 +161,31 @@ - + - + - + - - + + - + - - - - + + + + - + @@ -199,7 +199,7 @@ - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml index 6d5df7467..adc3da01e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -162,41 +162,41 @@ - + - + - + - - + + - + - - - - + + + + - + - - - - - + + + + + - + @@ -213,7 +213,7 @@ - + @@ -226,8 +226,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml index 6ddb0d681..1b2d8ffcb 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_frac_mem32K_frac_dsp36_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -162,47 +162,47 @@ - + - + - + - - + + - + - - - - + + + + - + - - - - - + + + + + - - + + - + @@ -218,11 +218,11 @@ - + - + @@ -239,7 +239,7 @@ - + @@ -252,8 +252,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml index b8c99a382..2733b0317 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -162,37 +162,37 @@ - + - + - + - - + + - + - - - - + + + + - + - - - - - + + + + + @@ -208,7 +208,7 @@ - + @@ -225,7 +225,7 @@ - + @@ -238,8 +238,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml index c0c1aa581..d900f0edb 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_chain_mem16K_aib_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -162,37 +162,37 @@ - + - + - + - - + + - + - - - - + + + + - + - - - - - + + + + + @@ -206,19 +206,19 @@ - + - - - - - + + + + + - + @@ -234,10 +234,10 @@ - + - + @@ -250,8 +250,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml index 26af034f5..b5439a151 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_column_chain_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -162,41 +162,41 @@ - + - + - + - - + + - + - - - - + + + + - + - - - - - + + + + + - + @@ -213,7 +213,7 @@ - + @@ -226,8 +226,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml index e10c12d27..b22057acb 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_chain_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -162,41 +162,41 @@ - + - + - + - - + + - + - - - - + + + + - + - - - - - + + + + + - + @@ -214,7 +214,7 @@ - + @@ -227,8 +227,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml index 8537cfc18..748f8ec48 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_40nm_openfpga.xml @@ -142,17 +142,17 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + - - - - + + + + - + @@ -167,41 +167,41 @@ - + - + - + - - + + - + - - - - + + + + - + - - - - - + + + + + - + @@ -220,7 +220,7 @@ - + @@ -233,8 +233,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml index b815842e7..4335c3ae4 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml @@ -142,17 +142,17 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + - - - - + + + + - + @@ -167,41 +167,41 @@ - + - + - + - - + + - + - - - - + + + + - + - - - - - + + + + + - + @@ -219,7 +219,7 @@ - + @@ -228,8 +228,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml index c74625e33..765bd94a1 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_spypad_40nm_openfpga.xml @@ -142,17 +142,17 @@ This is flip-flop with scan-chain feature. When the TESTEN is enabled, the data will be propagated form DI instead of D --> - + - - - - + + + + - + @@ -167,7 +167,7 @@ - + @@ -182,41 +182,41 @@ - + - + - + - - + + - + - - - - + + + + - + - - - - - + + + + + - + @@ -234,7 +234,7 @@ - + @@ -243,8 +243,8 @@ - - + + @@ -278,8 +278,8 @@ - - + + @@ -311,8 +311,8 @@ - - + + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml index e4a721acb..a0d9be879 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_behavioral_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -161,31 +161,31 @@ - + - + - + - - + + - + - - - - + + + + - + @@ -199,7 +199,7 @@ - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml index 51e8fca53..ef3bf9f21 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_local_encoder_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -161,31 +161,31 @@ - + - + - + - - + + - + - - - - + + + + - + @@ -199,7 +199,7 @@ - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml index 9ce18bc81..f9fcfe148 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_spyio_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -161,35 +161,35 @@ - + - + - + - - + + - + - + - - - + + + - + @@ -203,7 +203,7 @@ - + @@ -216,7 +216,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml index cfda3061f..588e88620 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_stdcell_mux_40nm_openfpga.xml @@ -131,15 +131,15 @@ - + - - + + - + @@ -153,31 +153,31 @@ - + - + - + - - + + - + - - - - + + + + - + @@ -191,7 +191,7 @@ - + @@ -204,7 +204,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml index e8980c6c3..da9767f10 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N10_tree_mux_40nm_openfpga.xml @@ -130,15 +130,15 @@ - + - - + + - + @@ -152,31 +152,31 @@ - + - + - + - - + + - + - - - - + + + + - + @@ -190,7 +190,7 @@ - + @@ -203,7 +203,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml index 74d1d9933..098e7ba2e 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -161,31 +161,31 @@ - + - + - + - - + + - + - - - - + + + + - + @@ -199,7 +199,7 @@ - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml index b0c8c6ba0..53dda3357 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_debuf_mux_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -161,31 +161,31 @@ - + - + - + - - + + - + - - - - + + + + - + @@ -199,7 +199,7 @@ - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml index 1cb12f465..f050bd8a7 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_inbuf_only_mux_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -161,31 +161,31 @@ - + - + - + - - + + - + - - - - + + + + - + @@ -199,7 +199,7 @@ - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml index 721fb6663..ec3f99c4d 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_local_encoder_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -161,31 +161,31 @@ - + - + - + - - + + - + - - - - + + + + - + @@ -199,7 +199,7 @@ - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml index 07b4e93d8..cab4ef22b 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_outbuf_only_mux_40nm_openfpga.xml @@ -139,15 +139,15 @@ - + - - + + - + @@ -161,31 +161,31 @@ - + - + - + - - + + - + - - - - + + + + - + @@ -199,7 +199,7 @@ - + @@ -212,7 +212,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml index da7c4b76b..e367ff8bb 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_stdcell_mux_40nm_openfpga.xml @@ -131,15 +131,15 @@ - + - - + + - + @@ -153,31 +153,31 @@ - + - + - + - - + + - + - - - - + + + + - + @@ -191,7 +191,7 @@ - + @@ -204,7 +204,7 @@ - + diff --git a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml index b39c7a999..0585bf591 100644 --- a/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k6_frac_N8_tree_mux_40nm_openfpga.xml @@ -130,15 +130,15 @@ - + - - + + - + @@ -152,31 +152,31 @@ - + - + - + - - + + - + - - - - + + + + - + @@ -190,7 +190,7 @@ - + @@ -203,7 +203,7 @@ - + diff --git a/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf b/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf new file mode 100644 index 000000000..364962203 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/fixed_device_support/config/task.conf @@ -0,0 +1,44 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fix_device_route_chan_width_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=2x2 +openfpga_vpr_route_chan_width=40 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf new file mode 100644 index 000000000..b96d8f648 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_reset/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf new file mode 100644 index 000000000..379ae0404 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_resetb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_resetb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf new file mode 100644 index 000000000..6c7ae7c75 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf new file mode 100644 index 000000000..288a3564a --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_set_reset/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf new file mode 100644 index 000000000..4a8222d91 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_chain_use_setb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/configuration_chain_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_setb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf new file mode 100644 index 000000000..399be683b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_ccff/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_ccff_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf new file mode 100644 index 000000000..2be6528e4 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_scff/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_scff_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf new file mode 100644 index 000000000..b5e82f32b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_reset/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf new file mode 100644 index 000000000..24751ed47 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_resetb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_resetb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf new file mode 100644 index 000000000..1f2a9bd45 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf new file mode 100644 index 000000000..548e37cb8 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_set_reset/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf new file mode 100644 index 000000000..793854774 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/configuration_frame_use_setb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_setb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf index 0d98afa11..04e7fef1b 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain/config/task.conf @@ -8,7 +8,6 @@ [GENERAL] run_engine=openfpga_shell -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml power_analysis = true spice_output=false @@ -18,7 +17,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf new file mode 100644 index 000000000..d3879a68f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_chain_use_set/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf index 3626d3e85..0ab4871ca 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame/config/task.conf @@ -17,7 +17,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf new file mode 100644 index 000000000..4b5763f69 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_configuration_frame_use_set/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf index e669edf34..05e3f475b 100644 --- a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank/config/task.conf @@ -17,7 +17,7 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf new file mode 100644 index 000000000..44494baf6 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/fast_memory_bank_use_set/config/task.conf @@ -0,0 +1,42 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf new file mode 100644 index 000000000..cb9ddbee7 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_reset/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf new file mode 100644 index 000000000..87ef8b32b --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_resetb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_resetb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf new file mode 100644 index 000000000..cf4341928 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_set_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf new file mode 100644 index 000000000..855e3156e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_set_reset/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf new file mode 100644 index 000000000..55af9d7cc --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/memory_bank_use_setb/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/full_testbench_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_setb_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf new file mode 100644 index 000000000..fb8de2067 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_chain/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf new file mode 100644 index 000000000..1cdffa78f --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_configuration_frame/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf new file mode 100644 index 000000000..26e5b6239 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/full_testbench/smart_fast_memory_bank/config/task.conf @@ -0,0 +1,34 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/fast_configuration_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_bank_use_both_set_reset_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n5_pattern_local_routing/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n5_pattern_local_routing/config/task.conf new file mode 100644 index 000000000..2a94ee552 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n5_pattern_local_routing/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N5_pattern_local_routing_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +external_fabric_key_file= + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.blif + +[SYNTHESIS_PARAM] +bench0_top = and2_latch +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v +bench0_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf index 89ba177b6..f88536f37 100644 --- a/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf +++ b/openfpga_flow/tasks/fpga_bitstream/load_external_architecture_bitstream/config/task.conf @@ -17,7 +17,7 @@ fpga_flow=vpr_blif [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/load_external_arch_bitstream_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_use_reset_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_external_arch_bitstream_file=${PATH:OPENFPGA_PATH}/openfpga_flow/arch_bitstreams/and2_k4_N4_tileable_40nm_bitstream.xml openfpga_vpr_device_layout=2x2 diff --git a/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml b/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml similarity index 66% rename from openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml rename to openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml index ceacbb3f2..29c20f59a 100644 --- a/openfpga/test_vpr_arch/k6_N10_tileable_40nm.xml +++ b/openfpga_flow/vpr_arch/k4_N5_tileable_pattern_local_routing_40nm.xml @@ -3,7 +3,7 @@ - 40 nm technology - General purpose logic block: - K = 6, N = 10 + K = 4, N = 5 - Routing architecture: L = 4, fc_in = 0.15, Fc_out = 0.1 Details on Modelling: @@ -41,21 +41,20 @@ - - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock - io.outpad io.inpad io.clock + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad - - + + @@ -71,6 +70,13 @@ + + + + + + + @@ -198,40 +203,31 @@ routing area up significantly, we estimate into the ~70% range. --> - - + + - - + + + - - - - - + + + + + + - - + + - - - 261e-12 - 261e-12 + 261e-12 261e-12 261e-12 @@ -247,23 +243,25 @@ - - + + - + - - + + + - - + + - - - + + + + @@ -278,18 +276,76 @@ Since all our outputs LUT outputs go to a BLE output, and have a delay of 25 ps to do so, we subtract 25 ps from the 100 ps delay of a feedback to get the part that should be marked on the crossbar. --> - - - + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - +