start transplanting fpga_verilog
This commit is contained in:
tangxifan
parent
85627dc128
commit
622c7826d1
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@ -2,6 +2,9 @@
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* This file includes functions that handles the file outputting
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* in OpenFPGA framework
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*******************************************************************/
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#include <sys/stat.h>
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#include <algorithm>
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/* Headers from vtrutil library */
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#include "vtr_log.h"
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@ -37,4 +40,114 @@ void check_file_stream(const char* fname,
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}
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}
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/********************************************************************
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* Format a directory path:
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* 1. Replace "\" with "/"
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* 2. add a "/" if the string does not end with a "/"
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*******************************************************************/
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std::string format_dir_path(const std::string& dir_path_to_format) {
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std::string formatted_dir_path = dir_path_to_format;
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char illegal_back_slash = '\\';
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char legal_back_slash = '/';
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#ifdef _WIN32
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/* For windows OS, replace any '/' with '\' */
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char illegal_back_slash = '/';
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char legal_back_slash = '\\';
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#endif
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/* Replace "\" with "/" */
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std::replace(formatted_dir_path.begin(), formatted_dir_path.end(), illegal_back_slash, legal_back_slash);
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/* Add a back slash the string is not ended like this! */
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if (legal_back_slash != formatted_dir_path.back()) {
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formatted_dir_path.push_back(legal_back_slash);
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}
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return formatted_dir_path;
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}
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/********************************************************************
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* Extract full file name from a full path of file
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* For example: <dir_path>/<file_name>
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* This function will return <file_name>
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********************************************************************/
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std::string find_path_file_name(const std::string& file_name) {
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char back_slash = '/';
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#ifdef _WIN32
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/* For windows OS, replace any '/' with '\' */
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char back_slash = '\\';
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#endif
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/* Find the last '/' in the string and return the left part */
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size_t found = file_name.rfind(back_slash);
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if (found != std::string::npos) {
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return file_name.substr(found + 1);
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}
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/* Not found. The input is the file name! Return the original string */
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return file_name;
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}
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/********************************************************************
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* Extract full directory path from a full path of file
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* For example: <dir_path>/<file_name>
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* This function will return <dir_path>
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********************************************************************/
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std::string find_path_dir_name(const std::string& file_name) {
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char back_slash = '/';
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#ifdef _WIN32
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/* For windows OS, replace any '/' with '\' */
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char back_slash = '\\';
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#endif
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/* Find the last '/' in the string and return the left part */
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size_t found = file_name.rfind(back_slash);
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if (found != std::string::npos) {
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return file_name.substr(0, found);
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}
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/* Not found, return an empty string */
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return std::string();
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}
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/********************************************************************
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* Create a directory with a given path
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********************************************************************/
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bool create_dir_path(const char* dir_path) {
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/* Give up if the path is empty */
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if (nullptr == dir_path) {
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VTR_LOG_ERROR("dir_path is empty and nothing is created.\n");
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return false;
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}
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/* Try to create a directory */
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int ret = mkdir(dir_path, S_IRWXU|S_IRWXG|S_IROTH|S_IXOTH);
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/* Analyze the return flag and output status */
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switch (ret) {
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case 0:
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VTR_LOG("Succeed to create directory '%s'\n",
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dir_path);
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return true;
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case -1:
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if (EEXIST == errno) {
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VTR_LOG_ERROR("Directory '%s' already exists. Will overwrite contents\n",
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dir_path);
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return true;
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}
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break;
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default:
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VTR_LOG_ERROR("Create directory '%s'...Failed!\n",
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dir_path);
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exit(1);
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return false;
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}
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return false;
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}
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} /* namespace openfpga ends */
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@ -17,6 +17,14 @@ bool valid_file_stream(std::fstream& fp);
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void check_file_stream(const char* fname,
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std::fstream& fp);
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std::string format_dir_path(const std::string& dir_path_to_format);
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std::string find_path_file_name(const std::string& file_name);
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std::string find_path_dir_name(const std::string& file_name);
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bool create_dir_path(const char* dir_path);
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} /* namespace openfpga ends */
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#endif
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@ -0,0 +1,118 @@
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/********************************************************************
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* This file include top-level function of FPGA-Verilog
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********************************************************************/
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/* Headers from vtrutil library */
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#include "vtr_log.h"
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#include "vtr_assert.h"
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#include "vtr_time.h"
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#include "circuit_library_utils.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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#include "device_rr_gsb.h"
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#include "verilog_constants.h"
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//#include "verilog_submodules.h"
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//#include "verilog_routing.h"
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//#include "verilog_submodules.h"
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//#include "verilog_grid.h"
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//#include "verilog_routing.h"
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//#include "verilog_top_module.h"
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/* Header file for this source file */
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#include "verilog_api.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Top-level function of FPGA-Verilog
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* This function will generate
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* 1. primitive modules required by the full fabric
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* which are LUTs, routing multiplexer, logic gates, transmission-gates etc.
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* 2. Routing modules, which are Switch Blocks (SBs) and Connection Blocks (CBs)
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* 3. Logic block modules, which are Configuration Logic Blocks (CLBs)
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* 4. FPGA module, which are the full FPGA fabric with configuration protocol
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* 5. A wrapper module, which encapsulate the FPGA module in a Verilog module which have the same port as the input benchmark
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* 6. Testbench, where a FPGA module is configured with a bitstream and then driven by input vectors
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* 7. Pre-configured testbench, which can skip the configuration phase and pre-configure the FPGA module. This testbench is created for quick verification and formal verification purpose.
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* 8. Verilog netlist including preprocessing flags and all the Verilog netlists that have been generated
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********************************************************************/
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void fabric_verilog(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const MuxLibrary& mux_lib,
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const DeviceGrid& grids,
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const DeviceRRGSB& device_rr_gsb,
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const std::string& output_directory,
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const bool& compress_routing,
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const bool& dump_explict_verilog,
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const bool& verbose) {
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vtr::ScopedStartFinishTimer timer("Generate Verilog netlists for FPGA fabric\n");
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std::string src_dir_path = format_dir_path(output_directory);
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/* Create directories */
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create_dir_path(src_dir_path.c_str());
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/* Sub directory under SRC directory to contain all the primitive block netlists */
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std::string submodule_dir_path = src_dir_path + std::string(DEFAULT_SUBMODULE_DIR_NAME);
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create_dir_path(submodule_dir_path.c_str());
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/* Sub directory under SRC directory to contain all the logic block netlists */
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std::string lb_dir_path = src_dir_path + std::string(DEFAULT_LB_DIR_NAME);
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create_dir_path(lb_dir_path.c_str());
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/* Sub directory under SRC directory to contain all the routing block netlists */
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std::string rr_dir_path = src_dir_path + std::string(DEFAULT_RR_DIR_NAME);
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create_dir_path(rr_dir_path.c_str());
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/* Print Verilog files containing preprocessing flags */
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//print_verilog_preprocessing_flags_netlist(std::string(src_dir_path),
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// vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
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//print_verilog_simulation_preprocessing_flags(std::string(src_dir_path),
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// vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
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/* Generate primitive Verilog modules, which are corner stones of FPGA fabric
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* Note that this function MUST be called before Verilog generation of
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* core logic (i.e., logic blocks and routing resources) !!!
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* This is because that this function will add the primitive Verilog modules to
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* the module manager.
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* Without the modules in the module manager, core logic generation is not possible!!!
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*/
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//print_verilog_submodules(module_manager, mux_lib, sram_verilog_orgz_info, src_dir_path.c_str(), submodule_dir_path.c_str(),
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// Arch, vpr_setup.FPGA_SPICE_Opts.SynVerilogOpts);
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/* Generate routing blocks */
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//if (true == compress_routing) {
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// print_verilog_unique_routing_modules(module_manager, device_rr_gsb,
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// src_dir_path, rr_dir_path,
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// dump_explicit_verilog);
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//} else {
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// VTR_ASSERT(false == compress_routing);
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// print_verilog_flatten_routing_modules(module_manager, device_rr_gsb,
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// src_dir_path, rr_dir_path,
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// dump_explicit_verilog);
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//}
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/* Generate grids */
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//print_verilog_grids(module_manager,
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// src_dir_path, lb_dir_path,
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// dump_explicit_verilog);
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/* Generate FPGA fabric */
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//print_verilog_top_module(module_manager,
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// std::string(vpr_setup.FileNameOpts.ArchFile),
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// src_dir_path,
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// dump_explicit_verilog);
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/* Given a brief stats on how many Verilog modules have been written to files */
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VTR_LOGV(verbose,
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"Outputted %lu Verilog modules in total\n",
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module_manager.num_modules());
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}
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} /* end namespace openfpga */
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#ifndef VERILOG_API_H
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#define VERILOG_API_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <string>
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#include <vector>
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#include "vpr_types.h"
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#include "mux_library.h"
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#include "circuit_library.h"
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#include "device_grid.h"
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#include "device_rr_gsb.h"
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#include "module_manager.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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void fabric_verilog(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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const MuxLibrary& mux_lib,
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const DeviceGrid& grids,
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const DeviceRRGSB& device_rr_gsb,
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const std::string& output_directory,
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const bool& compress_routing,
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const bool& dump_explict_verilog,
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const bool& verbose);
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} /* end namespace openfpga */
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#endif
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#ifndef VERILOG_CONSTANTS_H
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#define VERILOG_CONSTANTS_H
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/* global parameters for dumping synthesizable verilog */
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constexpr char* VERILOG_NETLIST_FILE_POSTFIX = ".v";
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constexpr float VERILOG_SIM_TIMESCALE = 1e-9; // Verilog Simulation time scale (minimum time unit) : 1ns
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constexpr char* VERILOG_TIMING_PREPROC_FLAG = "ENABLE_TIMING"; // the flag to enable timing definition during compilation
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constexpr char* VERILOG_SIGNAL_INIT_PREPROC_FLAG = "ENABLE_SIGNAL_INITIALIZATION"; // the flag to enable signal initialization during compilation
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constexpr char* VERILOG_FORMAL_VERIFICATGION_PREPROC_FLAG = "ENABLE_FORMAL_VERIFICATION"; // the flag to enable formal verification during compilation
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constexpr char* INITIAL_SIMULATION_FLAG = "INITIAL_SIMULATION"; // the flag to enable initial functional verification
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constexpr char* AUTOCHECKED_SIMULATION_FLAG = "AUTOCHECKED_SIMULATION"; // the flag to enable autochecked functional verification
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constexpr char* FORMAL_SIMULATION_FLAG = "FORMAL_SIMULATION"; // the flag to enable formal functional verification
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constexpr char* DEFAULT_LB_DIR_NAME = "lb/";
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constexpr char* DEFAULT_RR_DIR_NAME = "routing/";
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constexpr char* DEFAULT_SUBMODULE_DIR_NAME = "sub_module/";
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constexpr char* MODELSIM_SIMULATION_TIME_UNIT = "ms";
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// Icarus variables and flag
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constexpr char* ICARUS_SIMULATION_FLAG = "ICARUS_SIMULATOR"; // the flag to enable specific Verilog code in testbenches
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// End of Icarus variables and flag
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constexpr char* VERILOG_TOP_POSTFIX = "_top.v";
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constexpr char* DEFINES_VERILOG_FILE_NAME = "fpga_defines.v";
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constexpr char* DEFINES_VERILOG_SIMULATION_FILE_NAME = "define_simulation.v";
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constexpr char* SUBMODULE_VERILOG_FILE_NAME = "sub_module.v";
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constexpr char* LOGIC_BLOCK_VERILOG_FILE_NAME = "logic_blocks.v";
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constexpr char* LUTS_VERILOG_FILE_NAME = "luts.v";
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constexpr char* ROUTING_VERILOG_FILE_NAME = "routing.v";
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constexpr char* MUXES_VERILOG_FILE_NAME = "muxes.v";
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constexpr char* LOCAL_ENCODER_VERILOG_FILE_NAME = "local_encoder.v";
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constexpr char* MEMORIES_VERILOG_FILE_NAME = "memories.v";
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constexpr char* WIRES_VERILOG_FILE_NAME = "wires.v";
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constexpr char* ESSENTIALS_VERILOG_FILE_NAME = "inv_buf_passgate.v";
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constexpr char* CONFIG_PERIPHERAL_VERILOG_FILE_NAME = "config_peripherals.v";
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constexpr char* USER_DEFINED_TEMPLATE_VERILOG_FILE_NAME = "user_defined_templates.v";
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#endif
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#ifndef VERILOG_PORT_TYPES_H
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#define VERILOG_PORT_TYPES_H
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enum e_dump_verilog_port_type {
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VERILOG_PORT_INPUT,
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VERILOG_PORT_OUTPUT,
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VERILOG_PORT_INOUT,
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VERILOG_PORT_WIRE,
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VERILOG_PORT_REG,
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VERILOG_PORT_CONKT,
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NUM_VERILOG_PORT_TYPES
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};
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constexpr std::array<const char*, NUM_VERILOG_PORT_TYPES> VERILOG_PORT_TYPE_STRING = {{"input", "output", "inout", "wire", "reg", ""}}; /* string version of enum e_verilog_port_type */
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#endif
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