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bug fixed in SDC for CBs and SBs: remove useless module names

This commit is contained in:
tangxifan 2020-01-17 11:24:33 -07:00
parent 9e911cd288
commit 622ba9bb8c
3 changed files with 45 additions and 12 deletions
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20
vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/pnr_sdc_routing_writer.cpp
View File

@ -82,11 +82,11 @@ void print_pnr_sdc_constrain_sb_mux_timing(std::fstream& fp,
/* Find the starting points */
for (const ModulePortId& module_input_port : module_input_ports) {
/* Constrain a path */
print_pnr_sdc_constrain_module_port2port_timing(fp,
module_manager,
sb_module, module_input_port,
sb_module, module_output_port,
switch_delays[module_input_port]);
print_pnr_sdc_constrain_port2port_timing(fp,
module_manager,
sb_module, module_input_port,
sb_module, module_output_port,
switch_delays[module_input_port]);
}
}
@ -271,11 +271,11 @@ void print_pnr_sdc_constrain_cb_mux_timing(std::fstream& fp,
/* Find the starting points */
for (const ModulePortId& module_input_port : module_input_ports) {
/* Constrain a path */
print_pnr_sdc_constrain_module_port2port_timing(fp,
module_manager,
cb_module, module_input_port,
cb_module, module_output_port,
switch_delays[module_input_port]);
print_pnr_sdc_constrain_port2port_timing(fp,
module_manager,
cb_module, module_input_port,
cb_module, module_output_port,
switch_delays[module_input_port]);
}
}

29
vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.cpp
View File

@ -67,12 +67,16 @@ void print_pnr_sdc_constrain_max_delay(std::fstream& fp,
fp << "set_max_delay";
fp << " -from ";
fp << src_instance_name << "/";
if (!src_instance_name.empty()) {
fp << src_instance_name << "/";
}
fp << src_port_name;
fp << " -to ";
fp << des_instance_name << "/";
if (!des_instance_name.empty()) {
fp << des_instance_name << "/";
}
fp << des_port_name;
fp << " " << std::setprecision(10) << delay;
@ -100,6 +104,27 @@ void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp,
}
/********************************************************************
* Constrain a path between two ports of a module with a given timing value
* This function will NOT output the module name
* Note: this function uses set_max_delay !!!
*******************************************************************/
void print_pnr_sdc_constrain_port2port_timing(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& input_parent_module_id,
const ModulePortId& module_input_port_id,
const ModuleId& output_parent_module_id,
const ModulePortId& module_output_port_id,
const float& tmax) {
print_pnr_sdc_constrain_max_delay(fp,
std::string(),
generate_sdc_port(module_manager.module_port(input_parent_module_id, module_input_port_id)),
std::string(),
generate_sdc_port(module_manager.module_port(output_parent_module_id, module_output_port_id)),
tmax);
}
/********************************************************************
* Disable timing for a port
*******************************************************************/

8
vpr7_x2p/vpr/SRC/fpga_x2p/backend_assistant/sdc_writer_utils.h
View File

@ -26,6 +26,14 @@ void print_pnr_sdc_constrain_module_port2port_timing(std::fstream& fp,
const ModulePortId& module_output_port_id,
const float& tmax);
void print_pnr_sdc_constrain_port2port_timing(std::fstream& fp,
const ModuleManager& module_manager,
const ModuleId& input_parent_module_id,
const ModulePortId& module_input_port_id,
const ModuleId& output_parent_module_id,
const ModulePortId& module_output_port_id,
const float& tmax);
void print_sdc_disable_port_timing(std::fstream& fp,
const BasicPort& port);