From a1d3b439d38edcadc422374c828705ef268b96e6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 17:19:12 -0700 Subject: [PATCH 1/8] [Test] Add a new test case to define a global reset port from a global tile port --- .../global_tile_reset/config/task.conf | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf new file mode 100644 index 000000000..d1fa21689 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClkReset_cc_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClkReset_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = and2_latch +bench1_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= From 7a0a3398d46e14a12ed7f6234a53f3332b704b48 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 17:43:41 -0700 Subject: [PATCH 2/8] [Arch] Add new architecture to test global reset ports defined thru tile ports --- ...avel_io_skywater130nm_fdhd_cc_openfpga.xml | 255 +++++++ ...n_chain_nonLR_caravel_io_skywater130nm.xml | 689 ++++++++++++++++++ 2 files changed, 944 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml create mode 100644 openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml new file mode 100644 index 000000000..4765feea6 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -0,0 +1,255 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml new file mode 100644 index 000000000..e7db6fd94 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml @@ -0,0 +1,689 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io_top.outpad io_top.inpad + + + + + + + + + + + + io_right.outpad io_right.inpad + + + + + + + + + + + + io_bottom.outpad io_bottom.inpad + + + + + + + + + + + + io_left.outpad io_left.inpad + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + clb.clk clb.reset + clb.reg_in clb.sc_in clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i + clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i + clb.reg_out clb.sc_out + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 + 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 27a480b5f8c6bba8a72428f6c235c0141fa8ff32 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 17:45:54 -0700 Subject: [PATCH 3/8] [Test] arch name fix in the test case --- .../global_tile_ports/global_tile_reset/config/task.conf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf index d1fa21689..8fb18383e 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf @@ -17,11 +17,11 @@ fpga_flow=yosys_vpr [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_GlobalTileClkReset_cc_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_GlobalTileClkReset_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v From ad703ad85bd436c26aff3253bd7a6914ddbf29e4 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 17:52:39 -0700 Subject: [PATCH 4/8] [HDL] Add new gpio cell with protection circuitry --- .../openfpga_cell_library/verilog/gpio.v | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/openfpga_flow/openfpga_cell_library/verilog/gpio.v b/openfpga_flow/openfpga_cell_library/verilog/gpio.v index 87a4a4d01..1b3618ab2 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/gpio.v +++ b/openfpga_flow/openfpga_cell_library/verilog/gpio.v @@ -57,3 +57,23 @@ module EMBEDDED_IO ( assign SOC_DIR = FPGA_DIR; endmodule +//----------------------------------------------------- +// Function : An embedded I/O with an protection circuit +// which can force the I/O in input mode +// The enable signal IO_ISOL_N is active-low +//----------------------------------------------------- +module EMBEDDED_IO_ISOLN ( + input SOC_IN, // Input to drive the inpad signal + output SOC_OUT, // Output the outpad signal + output SOC_DIR, // Output the directionality + output FPGA_IN, // Input data to FPGA + input FPGA_OUT, // Output data from FPGA + input FPGA_DIR, // direction control + input IO_ISOL_N // Active-low signal to set the I/O in input mode +); + + assign FPGA_IN = IO_ISOL_N ? SOC_IN : 1'bz; + assign SOC_OUT = IO_ISOL_N ? FPGA_OUT : 1'bz; + // Direction signal is set to logic '0' when in input mode + assign SOC_DIR = IO_ISOL_N ? FPGA_DIR : 1'b0; +endmodule From ff53d2c37539187a6699fff62b2c1ae42ba07512 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 17:54:10 -0700 Subject: [PATCH 5/8] [HDL] Add new Scan-chain DFF cell --- .../openfpga_cell_library/verilog/dff.v | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v index 99bb50c85..e54950827 100644 --- a/openfpga_flow/openfpga_cell_library/verilog/dff.v +++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v @@ -332,6 +332,37 @@ end endmodule //End Of Module +//----------------------------------------------------- +// Function : D-type flip-flop with +// - asynchronous active high reset +// - scan-chain input +// - a scan-chain enable +//----------------------------------------------------- +module SDFFRQ ( + input RST, // Reset input + input CK, // Clock Input + input SE, // Scan-chain Enable + input D, // Data Input + input SI, // Scan-chain input + output Q // Q output +); +//------------Internal Variables-------- +reg q_reg; + +//-------------Code Starts Here--------- +always @ ( posedge CK or posedge RST) +if (RST) begin + q_reg <= 1'b0; +end else if (SE) begin + q_reg <= SI; +end else begin + q_reg <= D; +end + +assign Q = q_reg; + +endmodule //End Of Module + //----------------------------------------------------- // Function : D-type flip-flop with // - asynchronous active high reset From c7604ab94f7bcb8522388d18547b7d9af6fdde06 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 18:02:00 -0700 Subject: [PATCH 6/8] [Arch] Bug fix due to prog_reset port name conflicting with reserved words of OpenFPGA --- ...ter_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml index 4765feea6..c543b9fa7 100644 --- a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml +++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml @@ -181,7 +181,7 @@ - + From 179b0ce304ef8ffffa53de78eda2a1180303b3a3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 18:11:47 -0700 Subject: [PATCH 7/8] [Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile --- .../global_tile_ports/global_tile_reset/config/task.conf | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf index 8fb18383e..34876d407 100644 --- a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf @@ -36,3 +36,4 @@ bench1_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From 290ff028cd172bcb91f167ed3709039c7aa04892 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 30 Nov 2020 18:12:47 -0700 Subject: [PATCH 8/8] [Test] Add global_tile_reset test case to CI --- .github/workflows/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/basic_reg_test.sh b/.github/workflows/basic_reg_test.sh index c988c9a21..b3394c424 100755 --- a/.github/workflows/basic_reg_test.sh +++ b/.github/workflows/basic_reg_test.sh @@ -105,3 +105,4 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/bot echo -e "Testing global port definition from tiles"; python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs +python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_reset --debug --show_thread_logs