diff --git a/.github/workflows/basic_reg_test.sh b/.github/workflows/basic_reg_test.sh
index c988c9a21..b3394c424 100755
--- a/.github/workflows/basic_reg_test.sh
+++ b/.github/workflows/basic_reg_test.sh
@@ -105,3 +105,4 @@ python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/tile_organization/bot
echo -e "Testing global port definition from tiles";
python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_clock --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py basic_tests/global_tile_ports/global_tile_reset --debug --show_thread_logs
diff --git a/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
new file mode 100644
index 000000000..c543b9fa7
--- /dev/null
+++ b/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
@@ -0,0 +1,255 @@
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+ 10e-12
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+ 10e-12 5e-12
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+ 10e-12 5e-12
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diff --git a/openfpga_flow/openfpga_cell_library/verilog/dff.v b/openfpga_flow/openfpga_cell_library/verilog/dff.v
index 99bb50c85..e54950827 100644
--- a/openfpga_flow/openfpga_cell_library/verilog/dff.v
+++ b/openfpga_flow/openfpga_cell_library/verilog/dff.v
@@ -332,6 +332,37 @@ end
endmodule //End Of Module
+//-----------------------------------------------------
+// Function : D-type flip-flop with
+// - asynchronous active high reset
+// - scan-chain input
+// - a scan-chain enable
+//-----------------------------------------------------
+module SDFFRQ (
+ input RST, // Reset input
+ input CK, // Clock Input
+ input SE, // Scan-chain Enable
+ input D, // Data Input
+ input SI, // Scan-chain input
+ output Q // Q output
+);
+//------------Internal Variables--------
+reg q_reg;
+
+//-------------Code Starts Here---------
+always @ ( posedge CK or posedge RST)
+if (RST) begin
+ q_reg <= 1'b0;
+end else if (SE) begin
+ q_reg <= SI;
+end else begin
+ q_reg <= D;
+end
+
+assign Q = q_reg;
+
+endmodule //End Of Module
+
//-----------------------------------------------------
// Function : D-type flip-flop with
// - asynchronous active high reset
diff --git a/openfpga_flow/openfpga_cell_library/verilog/gpio.v b/openfpga_flow/openfpga_cell_library/verilog/gpio.v
index 87a4a4d01..1b3618ab2 100644
--- a/openfpga_flow/openfpga_cell_library/verilog/gpio.v
+++ b/openfpga_flow/openfpga_cell_library/verilog/gpio.v
@@ -57,3 +57,23 @@ module EMBEDDED_IO (
assign SOC_DIR = FPGA_DIR;
endmodule
+//-----------------------------------------------------
+// Function : An embedded I/O with an protection circuit
+// which can force the I/O in input mode
+// The enable signal IO_ISOL_N is active-low
+//-----------------------------------------------------
+module EMBEDDED_IO_ISOLN (
+ input SOC_IN, // Input to drive the inpad signal
+ output SOC_OUT, // Output the outpad signal
+ output SOC_DIR, // Output the directionality
+ output FPGA_IN, // Input data to FPGA
+ input FPGA_OUT, // Output data from FPGA
+ input FPGA_DIR, // direction control
+ input IO_ISOL_N // Active-low signal to set the I/O in input mode
+);
+
+ assign FPGA_IN = IO_ISOL_N ? SOC_IN : 1'bz;
+ assign SOC_OUT = IO_ISOL_N ? FPGA_OUT : 1'bz;
+ // Direction signal is set to logic '0' when in input mode
+ assign SOC_DIR = IO_ISOL_N ? FPGA_DIR : 1'b0;
+endmodule
diff --git a/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf
new file mode 100644
index 000000000..34876d407
--- /dev/null
+++ b/openfpga_flow/tasks/basic_tests/global_tile_ports/global_tile_reset/config/task.conf
@@ -0,0 +1,39 @@
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Configuration file for running experiments
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
+# Each job execute fpga_flow script on combination of architecture & benchmark
+# timeout_each_job is timeout for each job
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+[GENERAL]
+run_engine=openfpga_shell
+power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
+power_analysis = true
+spice_output=false
+verilog_output=true
+timeout_each_job = 20*60
+fpga_flow=yosys_vpr
+
+[OpenFPGA_SHELL]
+openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/global_tile_clock_example_script.openfpga
+openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N8_reset_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
+openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
+
+[ARCHITECTURES]
+arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
+
+[BENCHMARKS]
+bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
+bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v
+
+[SYNTHESIS_PARAM]
+bench0_top = and2
+bench0_chan_width = 300
+
+bench1_top = and2_latch
+bench1_chan_width = 300
+
+[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
+end_flow_with_test=
+vpr_fpga_verilog_formal_verification_top_netlist=
diff --git a/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
new file mode 100644
index 000000000..e7db6fd94
--- /dev/null
+++ b/openfpga_flow/vpr_arch/k4_frac_N8_tileable_reset_register_scan_chain_nonLR_caravel_io_skywater130nm.xml
@@ -0,0 +1,689 @@
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+ io_right.outpad io_right.inpad
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+ io_bottom.outpad io_bottom.inpad
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+ clb.clk clb.reset
+ clb.reg_in clb.sc_in clb.O[7:0] clb.I0 clb.I0i clb.I1 clb.I1i clb.I2 clb.I2i clb.I3 clb.I3i
+ clb.O[15:8] clb.I4 clb.I4i clb.I5 clb.I5i clb.I6 clb.I6i clb.I7 clb.I7i
+ clb.reg_out clb.sc_out
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