diff --git a/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf
index 6d22dd9f1..278b07b8f 100644
--- a/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf
+++ b/openfpga_flow/tasks/benchmark_sweep/vtr_benchmarks/config/task.conf
@@ -42,11 +42,11 @@ bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/blob_merge.v
 bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/ch_intrinsics.v
 bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq1.v
 bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/diffeq2.v
-# Require many different DPRAM modules to be added (each has a different address and data width)
+# Comment out due to high runtime 
 #bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/LU8PEEng.v
-# Require many different DPRAM modules to be added (each has a different address and data width)
+# Comment out due to high runtime 
 #bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/LU32PEEng.v
-# Require many different DPRAM modules to be added (each has a different address and data width)
+# Comment out due to high runtime 
 #bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mcml.v
 bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkDelayWorker32B.v
 bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/vtr_benchmark/mkPktMerge.v